Update ARMConstantPoolValue to not use a modifier string. Use an explicit

[oota-llvm.git] / lib / Target / ARM / ARMInstrVFP.td

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 65f640ecd1f3c048efe77d381cd34503fc246bc9..e0fb5808a87f0b020e5958b6e865337d1df9af28 100644 (file)
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -54,43 +54,21 @@ let canFoldAsLoad = 1, isReMaterializable = 1 in {
 
 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
                  IIC_fpLoad64, "vldr", ".64\t$Dd, $addr",
-                 [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]> {
-  // Instruction operands.
-  bits<5>  Dd;
-  bits<13> addr;
-
-  // Encode instruction operands.
-  let Inst{23}    = addr{8};      // U (add = (U == '1'))
-  let Inst{22}    = Dd{4};
-  let Inst{19-16} = addr{12-9};   // Rn
-  let Inst{15-12} = Dd{3-0};
-  let Inst{7-0}   = addr{7-0};    // imm8
-}
+                 [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>;
 
 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
                  IIC_fpLoad32, "vldr", ".32\t$Sd, $addr",
-                 [(set SPR:$Sd, (load addrmode5:$addr))]> {
-  // Instruction operands.
-  bits<5>  Sd;
-  bits<13> addr;
-
-  // Encode instruction operands.
-  let Inst{23}    = addr{8};      // U (add = (U == '1'))
-  let Inst{22}    = Sd{0};
-  let Inst{19-16} = addr{12-9};   // Rn
-  let Inst{15-12} = Sd{4-1};
-  let Inst{7-0}   = addr{7-0};    // imm8
-}
+                 [(set SPR:$Sd, (load addrmode5:$addr))]>;
 
 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
 
-def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
-                 IIC_fpStore64, "vstr", ".64\t$src, $addr",
-                 [(store (f64 DPR:$src), addrmode5:$addr)]>;
+def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
+                 IIC_fpStore64, "vstr", ".64\t$Dd, $addr",
+                 [(store (f64 DPR:$Dd), addrmode5:$addr)]>;
 
-def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
-                 IIC_fpStore32, "vstr", ".32\t$src, $addr",
-                 [(store SPR:$src, addrmode5:$addr)]>;
+def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
+                 IIC_fpStore32, "vstr", ".32\t$Sd, $addr",
+                 [(store SPR:$Sd, addrmode5:$addr)]>;
 
 //===----------------------------------------------------------------------===//
 //  Load / store multiple Instructions.
@@ -102,14 +80,16 @@ def VLDMD : AXDI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
                            reglist:$dsts, variable_ops),
                   IndexModeNone, IIC_fpLoad_m,
                   "vldm${amode}${p}\t$Rn, $dsts", "", []> {
-  let Inst{20} = 1;
+  let Inst{21} = 0;             // wback = (W == '1')
+  let Inst{20} = 1;             // Load
 }
 
 def VLDMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
                            reglist:$dsts, variable_ops),
                   IndexModeNone, IIC_fpLoad_m,
                   "vldm${amode}${p}\t$Rn, $dsts", "", []> {
-  let Inst{20} = 1;
+  let Inst{21} = 0;             // wback = (W == '1')
+  let Inst{20} = 1;             // Load
 }
 
 def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
@@ -117,7 +97,8 @@ def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
                       IndexModeUpd, IIC_fpLoad_mu,
                       "vldm${amode}${p}\t$Rn!, $dsts",
                       "$Rn = $wb", []> {
-  let Inst{20} = 1;
+  let Inst{21} = 1;             // wback = (W == '1')
+  let Inst{20} = 1;             // Load
 }
 
 def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
@@ -125,7 +106,8 @@ def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
                       IndexModeUpd, IIC_fpLoad_mu, 
                       "vldm${amode}${p}\t$Rn!, $dsts",
                       "$Rn = $wb", []> {
-  let Inst{20} = 1;
+  let Inst{21} = 1;             // wback = (W == '1')
+  let Inst{20} = 1;             // Load
 }
 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
 
@@ -135,14 +117,16 @@ def VSTMD : AXDI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
                            reglist:$srcs, variable_ops),
                   IndexModeNone, IIC_fpStore_m,
                   "vstm${amode}${p}\t$Rn, $srcs", "", []> {
-  let Inst{20} = 0;
+  let Inst{21} = 0;             // wback = (W == '1')
+  let Inst{20} = 0;             // Store
 }
 
 def VSTMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
                            reglist:$srcs, variable_ops), IndexModeNone,
                    IIC_fpStore_m,
                   "vstm${amode}${p}\t$Rn, $srcs", "", []> {
-  let Inst{20} = 0;
+  let Inst{21} = 0;             // wback = (W == '1')
+  let Inst{20} = 0;             // Store
 }
 
 def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
@@ -150,7 +134,8 @@ def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
                       IndexModeUpd, IIC_fpStore_mu,
                       "vstm${amode}${p}\t$Rn!, $srcs",
                       "$Rn = $wb", []> {
-  let Inst{20} = 0;
+  let Inst{21} = 1;             // wback = (W == '1')
+  let Inst{20} = 0;             // Store
 }
 
 def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
@@ -158,7 +143,8 @@ def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
                       IndexModeUpd, IIC_fpStore_mu,
                       "vstm${amode}${p}\t$Rn!, $srcs",
                       "$Rn = $wb", []> {
-  let Inst{20} = 0;
+  let Inst{21} = 1;             // wback = (W == '1')
+  let Inst{20} = 0;             // Store
 }
 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq