#define DEBUG_TYPE "jit"
#include "ARMJITInfo.h"
+#include "ARMInstrInfo.h"
+#include "ARMConstantPoolValue.h"
#include "ARMRelocations.h"
#include "ARMSubtarget.h"
#include "llvm/Function.h"
#include "llvm/CodeGen/MachineCodeEmitter.h"
#include "llvm/Config/alloca.h"
+#include "llvm/Support/Debug.h"
#include "llvm/Support/Streams.h"
#include "llvm/System/Memory.h"
#include <cstdlib>
// whole compilation callback doesn't exist as far as the caller is
// concerned, so we can't just preserve the callee saved regs.
"stmdb sp!, {r0, r1, r2, r3, lr}\n"
+#ifndef __SOFTFP__
+ "fstmfdd sp!, {d0, d1, d2, d3, d4, d5, d6, d7}\n"
+#endif
// The LR contains the address of the stub function on entry.
// pass it as the argument to the C part of the callback
"mov r0, lr\n"
// +--------+
// 1 | LR | Stub address (start of stub)
// 2-5 | R3..R0 | Saved registers (we need to preserve all regs)
+ // 6-20 | D0..D7 | Saved VFP registers
// +--------+
//
+#ifndef __SOFTFP__
+ // Restore VFP caller-saved registers.
+ "fldmfdd sp!, {d0, d1, d2, d3, d4, d5, d6, d7}\n"
+#endif
+ //
// We need to exchange the values in slots 0 and 1 so we can
// return to the address in slot 1 with the address in slot 0
// restored to the LR.
// stub with:
// ldr pc, [pc,#-4]
// <addr>
- bool ok = sys::Memory::setRangeWritable ((void*)StubAddr, 8);
- if (!ok)
- {
- cerr << "ERROR: Unable to mark stub writable\n";
- abort();
- }
- *(intptr_t *)StubAddr = 0xe51ff004;
+ if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) {
+ cerr << "ERROR: Unable to mark stub writable\n";
+ abort();
+ }
+ *(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4]
*(intptr_t *)(StubAddr+4) = NewVal;
- ok = sys::Memory::setRangeExecutable ((void*)StubAddr, 8);
- if (!ok)
- {
- cerr << "ERROR: Unable to mark stub executable\n";
- abort();
- }
+ if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) {
+ cerr << "ERROR: Unable to mark stub executable\n";
+ abort();
+ }
}
TargetJITInfo::LazyResolverFn
return ARMCompilationCallback;
}
+void *ARMJITInfo::emitGlobalValueIndirectSym(const GlobalValue *GV, void *Ptr,
+ MachineCodeEmitter &MCE) {
+ MCE.startGVStub(GV, 4, 4);
+ MCE.emitWordLE((intptr_t)Ptr);
+ void *PtrAddr = MCE.finishGVStub(GV);
+ addIndirectSymAddr(Ptr, (intptr_t)PtrAddr);
+ return PtrAddr;
+}
+
void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn,
MachineCodeEmitter &MCE) {
- unsigned addr = (intptr_t)Fn;
// If this is just a call to an external function, emit a branch instead of a
// call. The code is the same except for one bit of the last instruction.
if (Fn != (void*)(intptr_t)ARMCompilationCallback) {
- // branch to the corresponding function addr
- // the stub is 8-byte size and 4-aligned
- MCE.startFunctionStub(F, 8, 4);
- MCE.emitWordLE(0xe51ff004); // LDR PC, [PC,#-4]
- MCE.emitWordLE(addr); // addr of function
+ // Branch to the corresponding function addr.
+ if (IsPIC) {
+ // The stub is 8-byte size and 4-aligned.
+ intptr_t LazyPtr = getIndirectSymAddr(Fn);
+ if (!LazyPtr) {
+ // In PIC mode, the function stub is loading a lazy-ptr.
+ LazyPtr= (intptr_t)emitGlobalValueIndirectSym((GlobalValue*)F, Fn, MCE);
+ if (F)
+ DOUT << "JIT: Indirect symbol emitted at [" << LazyPtr << "] for GV '"
+ << F->getName() << "'\n";
+ else
+ DOUT << "JIT: Stub emitted at [" << LazyPtr
+ << "] for external function at '" << Fn << "'\n";
+ }
+ MCE.startGVStub(F, 16, 4);
+ intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
+ MCE.emitWordLE(0xe59fc004); // ldr pc, [pc, #+4]
+ MCE.emitWordLE(0xe08fc00c); // L_func$scv: add ip, pc, ip
+ MCE.emitWordLE(0xe59cf000); // ldr pc, [ip]
+ MCE.emitWordLE(LazyPtr - (Addr+4+8)); // func - (L_func$scv+8)
+ sys::Memory::InvalidateInstructionCache((void*)Addr, 16);
+ } else {
+ // The stub is 8-byte size and 4-aligned.
+ MCE.startGVStub(F, 8, 4);
+ intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
+ MCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4]
+ MCE.emitWordLE((intptr_t)Fn); // addr of function
+ sys::Memory::InvalidateInstructionCache((void*)Addr, 8);
+ }
} else {
// The compilation callback will overwrite the first two words of this
// stub with indirect branch instructions targeting the compiled code.
// This stub sets the return address to restart the stub, so that
// the new branch will be invoked when we come back.
//
- // branch and link to the compilation callback.
- // the stub is 16-byte size and 4-byte aligned.
- MCE.startFunctionStub(F, 16, 4);
+ // Branch and link to the compilation callback.
+ // The stub is 16-byte size and 4-byte aligned.
+ MCE.startGVStub(F, 16, 4);
+ intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
// Save LR so the callback can determine which stub called it.
// The compilation callback is responsible for popping this prior
// to returning.
- MCE.emitWordLE(0xe92d4000); // PUSH {lr}
- // Set the return address to go back to the start of this stub
- MCE.emitWordLE(0xe24fe00c); // SUB LR, PC, #12
- // Invoke the compilation callback
- MCE.emitWordLE(0xe51ff004); // LDR PC, [PC,#-4]
- // The address of the compilation callback
+ MCE.emitWordLE(0xe92d4000); // push {lr}
+ // Set the return address to go back to the start of this stub.
+ MCE.emitWordLE(0xe24fe00c); // sub lr, pc, #12
+ // Invoke the compilation callback.
+ MCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4]
+ // The address of the compilation callback.
MCE.emitWordLE((intptr_t)ARMCompilationCallback);
+ sys::Memory::InvalidateInstructionCache((void*)Addr, 16);
}
- return MCE.finishFunctionStub(F);
+ return MCE.finishGVStub(F);
+}
+
+intptr_t ARMJITInfo::resolveRelocDestAddr(MachineRelocation *MR) const {
+ ARM::RelocationType RT = (ARM::RelocationType)MR->getRelocationType();
+ switch (RT) {
+ default:
+ return (intptr_t)(MR->getResultPointer());
+ case ARM::reloc_arm_pic_jt:
+ // Destination address - jump table base.
+ return (intptr_t)(MR->getResultPointer()) - MR->getConstantVal();
+ case ARM::reloc_arm_jt_base:
+ // Jump table base address.
+ return getJumpTableBaseAddr(MR->getJumpTableIndex());
+ case ARM::reloc_arm_cp_entry:
+ case ARM::reloc_arm_vfp_cp_entry:
+ // Constant pool entry address.
+ return getConstantPoolEntryAddr(MR->getConstantPoolIndex());
+ case ARM::reloc_arm_machine_cp_entry: {
+ ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)MR->getConstantVal();
+ assert((!ACPV->hasModifier() && !ACPV->mustAddCurrentAddress()) &&
+ "Can't handle this machine constant pool entry yet!");
+ intptr_t Addr = (intptr_t)(MR->getResultPointer());
+ Addr -= getPCLabelAddr(ACPV->getLabelId()) + ACPV->getPCAdjustment();
+ return Addr;
+ }
+ }
}
/// relocate - Before the JIT can run a block of code that has been emitted,
unsigned NumRelocs, unsigned char* GOTBase) {
for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
void *RelocPos = (char*)Function + MR->getMachineCodeOffset();
- ARM::RelocationType RT = (ARM::RelocationType)MR->getRelocationType();
- // If this is a constpool relocation, get the address of the
- // constpool_entry instruction.
- intptr_t ResultPtr = (RT == ARM::reloc_arm_cp_entry)
- ? getConstantPoolEntryAddr(MR->getConstantPoolIndex())
- : (intptr_t)MR->getResultPointer();
+ intptr_t ResultPtr = resolveRelocDestAddr(MR);
switch ((ARM::RelocationType)MR->getRelocationType()) {
case ARM::reloc_arm_cp_entry:
+ case ARM::reloc_arm_vfp_cp_entry:
case ARM::reloc_arm_relative: {
// It is necessary to calculate the correct PC relative value. We
// subtract the base addr from the target addr to form a byte offset.
- ResultPtr = ResultPtr-(intptr_t)RelocPos-8;
+ ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
// If the result is positive, set bit U(23) to 1.
if (ResultPtr >= 0)
- *((unsigned*)RelocPos) |= 1 << 23;
+ *((intptr_t*)RelocPos) |= 1 << ARMII::U_BitShift;
else {
- // otherwise, obtain the absolute value and set
- // bit U(23) to 0.
- ResultPtr *= -1;
- *((unsigned*)RelocPos) &= 0xFF7FFFFF;
+ // Otherwise, obtain the absolute value and set bit U(23) to 0.
+ *((intptr_t*)RelocPos) &= ~(1 << ARMII::U_BitShift);
+ ResultPtr = - ResultPtr;
}
- // set the immed value calculated
- *((unsigned*)RelocPos) |= (unsigned)ResultPtr;
- // set register Rn to PC
- *((unsigned*)RelocPos) |= 0xF << 16;
+ // Set the immed value calculated.
+ // VFP immediate offset is multiplied by 4.
+ if (MR->getRelocationType() == ARM::reloc_arm_vfp_cp_entry)
+ ResultPtr = ResultPtr >> 2;
+ *((intptr_t*)RelocPos) |= ResultPtr;
+ // Set register Rn to PC.
+ *((intptr_t*)RelocPos) |=
+ ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
break;
}
+ case ARM::reloc_arm_pic_jt:
+ case ARM::reloc_arm_machine_cp_entry:
case ARM::reloc_arm_absolute: {
- *((unsigned*)RelocPos) += (unsigned)ResultPtr;
+ // These addresses have already been resolved.
+ *((intptr_t*)RelocPos) |= (intptr_t)ResultPtr;
break;
}
case ARM::reloc_arm_branch: {
// byte offset, which must be inside the range -33554432 and +33554428.
// Then, we set the signed_immed_24 field of the instruction to bits
// [25:2] of the byte offset. More details ARM-ARM p. A4-11.
- ResultPtr = ResultPtr-(intptr_t)RelocPos-8;
+ ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
ResultPtr = (ResultPtr & 0x03FFFFFC) >> 2;
assert(ResultPtr >= -33554432 && ResultPtr <= 33554428);
- *((unsigned*)RelocPos) |= ResultPtr;
+ *((intptr_t*)RelocPos) |= ResultPtr;
+ break;
+ }
+ case ARM::reloc_arm_jt_base: {
+ // JT base - (instruction addr + 8)
+ ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
+ *((intptr_t*)RelocPos) |= ResultPtr;
break;
}
}
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