add isTerminatortto b and bcond

[oota-llvm.git] / lib / Target / ARM / ARMRegisterInfo.cpp

diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index d5f6caaa4ced7c7c4510f7f368bef94b77b6b18c..b313d548578e2bfef16e6a73732f257ac702129e 100644 (file)
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -47,8 +47,17 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I,
                                      unsigned DestReg, unsigned SrcReg,
                                      const TargetRegisterClass *RC) const {
-  assert (RC == ARM::IntRegsRegisterClass);
-  BuildMI(MBB, I, ARM::MOV, 1, DestReg).addReg(SrcReg);
+  assert(RC == ARM::IntRegsRegisterClass ||
+         RC == ARM::FPRegsRegisterClass  ||
+         RC == ARM::DFPRegsRegisterClass);
+
+  if (RC == ARM::IntRegsRegisterClass)
+    BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
+      .addImm(ARMShift::LSL);
+  else if (RC == ARM::FPRegsRegisterClass)
+    BuildMI(MBB, I, ARM::FCPYS, 1, DestReg).addReg(SrcReg);
+  else
+    BuildMI(MBB, I, ARM::FCPYD, 1, DestReg).addReg(SrcReg);
 }
 
 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
@@ -97,8 +106,8 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
 
   int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
 
-  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
-  assert (MI.getOperand(OffIdx).getImmedValue() == 0);
+  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
+               MI.getOperand(OffIdx).getImmedValue();
 
   unsigned StackSize = MF.getFrameInfo()->getStackSize();
 
@@ -114,7 +123,8 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
     // Insert a set of r12 with the full address
     // r12 = r13 + offset
     MachineBasicBlock *MBB2 = MI.getParent();
-    BuildMI(*MBB2, II, ARM::ADD, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
+    BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(ARM::R13).addImm(Offset)
+           .addImm(0).addImm(ARMShift::LSL);
 
     // Replace the FrameIndex with r12
     MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
@@ -137,10 +147,14 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
     NumBytes += MFI->getMaxCallFrameSize();
   }
 
+  // Align to 8 bytes
+  NumBytes = ((NumBytes + 7) / 8) * 8;
+
   MFI->setStackSize(NumBytes);
 
   //sub sp, sp, #NumBytes
-  BuildMI(MBB, MBBI, ARM::SUB, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
+  BuildMI(MBB, MBBI, ARM::SUB, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
+         .addImm(0).addImm(ARMShift::LSL);
 }
 
 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
@@ -153,7 +167,8 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
   int          NumBytes = (int) MFI->getStackSize();
 
   //add sp, sp, #NumBytes
-  BuildMI(MBB, MBBI, ARM::ADD, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
+  BuildMI(MBB, MBBI, ARM::ADD, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
+         .addImm(0).addImm(ARMShift::LSL);
 }
 
 unsigned ARMRegisterInfo::getRARegister() const {