The BLX instruction is encoded differently than the BL, because why not? In

[oota-llvm.git] / lib / Target / ARM / ARMRegisterInfo.cpp

diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 007b2914a136834d36b72f9e399e3b9da0b55bb2..d5bc3f60b01a9026675ba914d0c2323b0abbfbaa 100644 (file)
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -2,123 +2,40 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the "Instituto Nokia de Tecnologia" and
-// is distributed under the University of Illinois Open Source
+// This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
-// This file contains the ARM implementation of the MRegisterInfo class.
+// This file contains the ARM implementation of the TargetRegisterInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARM.h"
+#include "ARMAddressingModes.h"
+#include "ARMBaseInstrInfo.h"
+#include "ARMInstrInfo.h"
+#include "ARMMachineFunctionInfo.h"
 #include "ARMRegisterInfo.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineFunction.h"
+#include "ARMSubtarget.h"
+#include "llvm/Constants.h"
+#include "llvm/DerivedTypes.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineLocation.h"
-#include "llvm/Type.h"
-#include "llvm/ADT/STLExtras.h"
-#include <iostream>
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Target/TargetFrameInfo.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SmallVector.h"
 using namespace llvm;
 
-ARMRegisterInfo::ARMRegisterInfo()
-  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
-}
-
-void ARMRegisterInfo::
-storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                    unsigned SrcReg, int FI,
-                    const TargetRegisterClass *RC) const {
-  // On the order of operands here: think "[FI + 0] = SrcReg".
-  assert (RC == ARM::IntRegsRegisterClass);
-  BuildMI(MBB, I, ARM::str, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
-}
-
-void ARMRegisterInfo::
-loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                     unsigned DestReg, int FI,
-                     const TargetRegisterClass *RC) const {
-  assert (RC == ARM::IntRegsRegisterClass);
-  BuildMI(MBB, I, ARM::ldr, 2, DestReg).addFrameIndex(FI).addImm(0);
-}
-
-void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator I,
-                                     unsigned DestReg, unsigned SrcReg,
-                                     const TargetRegisterClass *RC) const {
-  assert (RC == ARM::IntRegsRegisterClass);
-  BuildMI(MBB, I, ARM::movrr, 1, DestReg).addReg(SrcReg);
+ARMRegisterInfo::ARMRegisterInfo(const ARMBaseInstrInfo &tii,
+                                 const ARMSubtarget &sti)
+  : ARMBaseRegisterInfo(tii, sti) {
 }
-
-MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
-                                                   unsigned OpNum,
-                                                   int FI) const {
-  return NULL;
-}
-
-const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const {
-  static const unsigned CalleeSaveRegs[] = { 0 };
-  return CalleeSaveRegs;
-}
-
-const TargetRegisterClass* const *
-ARMRegisterInfo::getCalleeSaveRegClasses() const {
-  static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
-  return CalleeSaveRegClasses;
-}
-
-void ARMRegisterInfo::
-eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
-                              MachineBasicBlock::iterator I) const {
-  MBB.erase(I);
-}
-
-void
-ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
-  MachineInstr &MI = *II;
-  MachineBasicBlock &MBB = *MI.getParent();
-  MachineFunction &MF = *MBB.getParent();
-
-  assert (MI.getOpcode() == ARM::movri);
-
-  unsigned FrameIdx = 1;
-
-  int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
-
-  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
-
-  unsigned StackSize = MF.getFrameInfo()->getStackSize();
-
-  Offset += StackSize;
-
-  // Insert a set of r12 with the full address
-  // r12 = r13 + offset
-  MachineBasicBlock *MBB2 = MI.getParent();
-  BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
-
-  // Replace the FrameIndex with r12
-  MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
-}
-
-void ARMRegisterInfo::
-processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
-
-void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
-}
-
-void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
-                                  MachineBasicBlock &MBB) const {
-}
-
-unsigned ARMRegisterInfo::getRARegister() const {
-  return ARM::R14;
-}
-
-unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
-  return ARM::R13;
-}
-
-#include "ARMGenRegisterInfo.inc"
-