let SubRegClassList = [SPR, SPR, SPR, SPR, DPR_VFP2, DPR_VFP2];
}
-// Subset of QPR that have 32-bit SPR subregs.
-def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
- 128,
- [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]> {
- let SubRegClassList = [SPR, SPR, SPR, SPR, DPR, DPR];
-}
-
// Condition code registers.
def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;