let SubRegs = subregs;
}
-class ARMFReg<bits<5> num, string n> : Register<n> {
- field bits<5> Num;
+class ARMFReg<bits<6> num, string n> : Register<n> {
+ field bits<6> Num;
let Namespace = "ARM";
}
def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;
def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
+def SDummy : ARMFReg<63, "sINVALID">;
// Aliases of the F* registers used to hold 64-bit fp values (doubles)
def D0 : ARMReg< 0, "d0", [S0, S1]>;
-def D1 : ARMReg< 1, "d1", [S2, S3]>;
+def D1 : ARMReg< 1, "d1", [S2, S3]>;
def D2 : ARMReg< 2, "d2", [S4, S5]>;
def D3 : ARMReg< 3, "d3", [S6, S7]>;
def D4 : ARMReg< 4, "d4", [S8, S9]>;
// Advanced SIMD (NEON) defines 16 quad-word aliases
def Q0 : ARMReg< 0, "q0", [D0, D1]>;
-def Q1 : ARMReg< 1, "q1", [D2, D3]>;
+def Q1 : ARMReg< 1, "q1", [D2, D3]>;
def Q2 : ARMReg< 2, "q2", [D4, D5]>;
def Q3 : ARMReg< 3, "q3", [D6, D7]>;
def Q4 : ARMReg< 4, "q4", [D8, D9]>;
def Q14 : ARMReg<14, "q14", [D28, D29]>;
def Q15 : ARMReg<15, "q15", [D30, D31]>;
-// Aliases for superclasses of NEON quad registers.
-def Q2_0: ARMReg<0, "q2_0", [Q0, Q1]>;
-def Q2_1: ARMReg<1, "q2_1", [Q2, Q3]>;
-def Q2_2: ARMReg<2, "q2_2", [Q4, Q5]>;
-def Q2_3: ARMReg<3, "q2_3", [Q6, Q7]>;
-def Q2_4: ARMReg<4, "q2_4", [Q8, Q9]>;
-def Q2_5: ARMReg<5, "q2_5", [Q10, Q11]>;
-def Q2_6: ARMReg<6, "q2_6", [Q12, Q13]>;
-def Q2_7: ARMReg<7, "q2_7", [Q14, Q15]>;
-
-def Q4_0: ARMReg<0, "q4_0", [Q2_0, Q2_1]>;
-def Q4_1: ARMReg<1, "q4_1", [Q2_2, Q2_3]>;
-def Q4_2: ARMReg<2, "q4_2", [Q2_4, Q2_5]>;
-def Q4_3: ARMReg<3, "q4_3", [Q2_6, Q2_7]>;
-
// Current Program Status Register.
-def CPSR : ARMReg<0, "cpsr">;
+def CPSR : ARMReg<0, "cpsr">;
+
+def FPSCR : ARMReg<1, "fpscr">;
// Register classes.
//
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
}];
- // FIXME: We are reserving r12 in case the PEI needs to use it to
- // generate large stack offset. Make it available once we have register
- // scavenging. Similarly r3 is reserved in Thumb mode for now.
let MethodBodies = [{
// FP is R11, R9 is available.
static const unsigned ARM_GPR_AO_1[] = {
ARM::R4, ARM::R5, ARM::R6,
ARM::R8, ARM::R10,ARM::R11,
ARM::R7 };
+ // FP is R7, R9 is available as callee-saved register.
+ // This is used by non-Darwin platform in Thumb mode.
+ static const unsigned ARM_GPR_AO_5[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6,
+ ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 };
+
+ // For Thumb1 mode, we don't want to allocate hi regs at all, as we
+ // don't know how to spill them. If we make our prologue/epilogue code
+ // smarter at some point, we can go back to using the above allocation
+ // orders for the Thumb1 instructions that know how to use hi regs.
+ static const unsigned THUMB_GPR_AO[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
GPRClass::iterator
GPRClass::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
+ if (Subtarget.isThumb1Only())
+ return THUMB_GPR_AO;
if (Subtarget.isTargetDarwin()) {
if (Subtarget.isR9Reserved())
return ARM_GPR_AO_4;
} else {
if (Subtarget.isR9Reserved())
return ARM_GPR_AO_2;
+ else if (Subtarget.isThumb())
+ return ARM_GPR_AO_5;
else
return ARM_GPR_AO_1;
}
const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
GPRClass::iterator I;
+ if (Subtarget.isThumb1Only()) {
+ I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
+ // Mac OS X requires FP not to be clobbered for backtracing purpose.
+ return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
+ }
+
if (Subtarget.isTargetDarwin()) {
if (Subtarget.isR9Reserved())
I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
} else {
if (Subtarget.isR9Reserved())
I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
+ else if (Subtarget.isThumb())
+ I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
else
I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
}
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
}];
- // FIXME: We are reserving r3 in Thumb mode in case the PEI needs to use it
- // to generate large stack offset. Make it available once we have register
- // scavenging.
let MethodBodies = [{
static const unsigned THUMB_tGPR_AO[] = {
- ARM::R0, ARM::R1, ARM::R2,
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
// FP is R7, only low registers available.
S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22,
S23, S24, S25, S26, S27, S28, S29, S30, S31]>;
+// Subset of SPR which can be used as a source of NEON scalars for 16-bit
+// operations
+def SPR_8 : RegisterClass<"ARM", [f32], 32,
+ [S0, S1, S2, S3, S4, S5, S6, S7,
+ S8, S9, S10, S11, S12, S13, S14, S15]>;
+
+// Dummy f32 regclass to represent impossible subreg indices.
+def SPR_INVALID : RegisterClass<"ARM", [f32], 32, [SDummy]> {
+ let CopyCost = -1;
+}
+
// Scalar double precision floating point / generic 64-bit vector register
// class.
// ARM requires only word alignment for double. It's more performant if it
// is double-word alignment though.
def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
[D0, D1, D2, D3, D4, D5, D6, D7,
- D8, D9, D10, D11, D12, D13, D14, D15]> {
- let SubRegClassList = [SPR, SPR];
+ D8, D9, D10, D11, D12, D13, D14, D15,
+ D16, D17, D18, D19, D20, D21, D22, D23,
+ D24, D25, D26, D27, D28, D29, D30, D31]> {
+ let SubRegClassList = [SPR_INVALID, SPR_INVALID];
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
// VFP2
- static const unsigned ARM_DPR_VFP2[] = {
- ARM::D0, ARM::D1, ARM::D2, ARM::D3,
- ARM::D4, ARM::D5, ARM::D6, ARM::D7,
- ARM::D8, ARM::D9, ARM::D10, ARM::D11,
+ static const unsigned ARM_DPR_VFP2[] = {
+ ARM::D0, ARM::D1, ARM::D2, ARM::D3,
+ ARM::D4, ARM::D5, ARM::D6, ARM::D7,
+ ARM::D8, ARM::D9, ARM::D10, ARM::D11,
ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
// VFP3
static const unsigned ARM_DPR_VFP3[] = {
- ARM::D0, ARM::D1, ARM::D2, ARM::D3,
- ARM::D4, ARM::D5, ARM::D6, ARM::D7,
- ARM::D8, ARM::D9, ARM::D10, ARM::D11,
+ ARM::D0, ARM::D1, ARM::D2, ARM::D3,
+ ARM::D4, ARM::D5, ARM::D6, ARM::D7,
+ ARM::D8, ARM::D9, ARM::D10, ARM::D11,
ARM::D12, ARM::D13, ARM::D14, ARM::D15,
- ARM::D16, ARM::D17, ARM::D18, ARM::D15,
+ ARM::D16, ARM::D17, ARM::D18, ARM::D19,
ARM::D20, ARM::D21, ARM::D22, ARM::D23,
ARM::D24, ARM::D25, ARM::D26, ARM::D27,
ARM::D28, ARM::D29, ARM::D30, ARM::D31 };
}];
}
+// Subset of DPR that are accessible with VFP2 (and so that also have
+// 32-bit SPR subregs).
+def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
+ [D0, D1, D2, D3, D4, D5, D6, D7,
+ D8, D9, D10, D11, D12, D13, D14, D15]> {
+ let SubRegClassList = [SPR, SPR];
+}
+
+// Subset of DPR which can be used as a source of NEON scalars for 16-bit
+// operations
+def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
+ [D0, D1, D2, D3, D4, D5, D6, D7]> {
+ let SubRegClassList = [SPR_8, SPR_8];
+}
+
// Generic 128-bit vector register class.
def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15]> {
- let SubRegClassList = [SPR, SPR, SPR, SPR, DPR, DPR];
+ let SubRegClassList = [SPR_INVALID, SPR_INVALID, SPR_INVALID, SPR_INVALID,
+ DPR, DPR];
}
-// Vector register class for NEON vector structures occupying either 3 or 4
-// DPR registers.
-def Q2PR: RegisterClass<"ARM", [v24i8, v12i16, v6i32, v3i64, v6f32,
- v32i8, v16i16, v8i32, v4i64, v8f32], 256,
- [Q2_0, Q2_1, Q2_2, Q2_3, Q2_4, Q2_5, Q2_6, Q2_7]> {
- let SubRegClassList = [SPR, SPR, SPR, SPR, SPR, SPR, SPR, SPR,
- DPR, DPR, DPR, DPR, QPR, QPR];
-}
-
-// Vector register class for NEON vector structures occupying either 6 or 8
-// DPR registers.
-def Q4PR: RegisterClass<"ARM", [v48i8, v24i16, v12i32, v6i64, v12f32,
- v64i8, v32i16, v16i32, v8i64, v16f32], 512,
- [Q4_0, Q4_1, Q4_2, Q4_3]> {
- let SubRegClassList = [SPR, SPR, SPR, SPR, SPR, SPR, SPR, SPR,
- SPR, SPR, SPR, SPR, SPR, SPR, SPR, SPR,
- DPR, DPR, DPR, DPR, DPR, DPR, DPR, DPR,
- QPR, QPR, QPR, QPR, Q2PR, Q2PR];
+// Subset of QPR that have 32-bit SPR subregs.
+def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
+ 128,
+ [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]> {
+ let SubRegClassList = [SPR, SPR, SPR, SPR, DPR_VFP2, DPR_VFP2];
}
// Condition code registers.
Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
[D1, D3, D5, D7, D9, D11, D13, D15,
D17, D19, D21, D23, D25, D27, D29, D31]>;
-
-// S sub-registers of Q2 registers.
-def : SubRegSet<1, [Q2_0, Q2_1, Q2_2, Q2_3], [S0, S8, S16, S24]>;
-def : SubRegSet<2, [Q2_0, Q2_1, Q2_2, Q2_3], [S1, S9, S17, S25]>;
-def : SubRegSet<3, [Q2_0, Q2_1, Q2_2, Q2_3], [S2, S10, S18, S26]>;
-def : SubRegSet<4, [Q2_0, Q2_1, Q2_2, Q2_3], [S3, S11, S19, S27]>;
-def : SubRegSet<5, [Q2_0, Q2_1, Q2_2, Q2_3], [S4, S12, S20, S28]>;
-def : SubRegSet<6, [Q2_0, Q2_1, Q2_2, Q2_3], [S5, S13, S21, S29]>;
-def : SubRegSet<7, [Q2_0, Q2_1, Q2_2, Q2_3], [S6, S14, S22, S30]>;
-def : SubRegSet<8, [Q2_0, Q2_1, Q2_2, Q2_3], [S7, S15, S23, S31]>;
-
-// D sub-registers of Q2 registers.
-def : SubRegSet<9, [Q2_0, Q2_1, Q2_2, Q2_3, Q2_4, Q2_5, Q2_6, Q2_7],
- [D0, D4, D8, D12, D16, D20, D24, D28]>;
-def : SubRegSet<10, [Q2_0, Q2_1, Q2_2, Q2_3, Q2_4, Q2_5, Q2_6, Q2_7],
- [D1, D5, D9, D13, D17, D21, D25, D29]>;
-def : SubRegSet<11, [Q2_0, Q2_1, Q2_2, Q2_3, Q2_4, Q2_5, Q2_6, Q2_7],
- [D2, D6, D10, D14, D18, D22, D26, D30]>;
-def : SubRegSet<12, [Q2_0, Q2_1, Q2_2, Q2_3, Q2_4, Q2_5, Q2_6, Q2_7],
- [D3, D7, D11, D15, D19, D23, D27, D31]>;
-
-// Q sub-registers of Q2 registers.
-def : SubRegSet<13, [Q2_0, Q2_1, Q2_2, Q2_3, Q2_4, Q2_5, Q2_6, Q2_7],
- [Q0, Q2, Q4, Q6, Q8, Q10, Q12, Q14]>;
-def : SubRegSet<14, [Q2_0, Q2_1, Q2_2, Q2_3, Q2_4, Q2_5, Q2_6, Q2_7],
- [Q1, Q3, Q5, Q7, Q9, Q11, Q13, Q15]>;
-
-// S sub-registers of Q4 registers.
-def : SubRegSet<1, [Q4_0, Q4_1], [S0, S16]>;
-def : SubRegSet<2, [Q4_0, Q4_1], [S1, S17]>;
-def : SubRegSet<3, [Q4_0, Q4_1], [S2, S18]>;
-def : SubRegSet<4, [Q4_0, Q4_1], [S3, S19]>;
-def : SubRegSet<5, [Q4_0, Q4_1], [S4, S20]>;
-def : SubRegSet<6, [Q4_0, Q4_1], [S5, S21]>;
-def : SubRegSet<7, [Q4_0, Q4_1], [S6, S22]>;
-def : SubRegSet<8, [Q4_0, Q4_1], [S7, S23]>;
-def : SubRegSet<9, [Q4_0, Q4_1], [S8, S24]>;
-def : SubRegSet<10, [Q4_0, Q4_1], [S9, S25]>;
-def : SubRegSet<11, [Q4_0, Q4_1], [S10, S26]>;
-def : SubRegSet<12, [Q4_0, Q4_1], [S11, S27]>;
-def : SubRegSet<13, [Q4_0, Q4_1], [S12, S28]>;
-def : SubRegSet<14, [Q4_0, Q4_1], [S13, S29]>;
-def : SubRegSet<15, [Q4_0, Q4_1], [S14, S30]>;
-def : SubRegSet<16, [Q4_0, Q4_1], [S15, S31]>;
-
-// D sub-registers of Q4 registers.
-def : SubRegSet<17, [Q4_0, Q4_1, Q4_2, Q4_3], [D0, D8, D16, D24]>;
-def : SubRegSet<18, [Q4_0, Q4_1, Q4_2, Q4_3], [D1, D9, D17, D25]>;
-def : SubRegSet<19, [Q4_0, Q4_1, Q4_2, Q4_3], [D2, D10, D18, D26]>;
-def : SubRegSet<20, [Q4_0, Q4_1, Q4_2, Q4_3], [D3, D11, D19, D27]>;
-def : SubRegSet<21, [Q4_0, Q4_1, Q4_2, Q4_3], [D4, D12, D20, D28]>;
-def : SubRegSet<22, [Q4_0, Q4_1, Q4_2, Q4_3], [D5, D13, D21, D29]>;
-def : SubRegSet<23, [Q4_0, Q4_1, Q4_2, Q4_3], [D6, D14, D22, D30]>;
-def : SubRegSet<24, [Q4_0, Q4_1, Q4_2, Q4_3], [D7, D15, D23, D31]>;
-
-// Q sub-registers of Q4 registers.
-def : SubRegSet<25, [Q4_0, Q4_1, Q4_2, Q4_3], [Q0, Q4, Q8, Q12]>;
-def : SubRegSet<26, [Q4_0, Q4_1, Q4_2, Q4_3], [Q1, Q5, Q9, Q13]>;
-def : SubRegSet<27, [Q4_0, Q4_1, Q4_2, Q4_3], [Q2, Q6, Q10, Q14]>;
-def : SubRegSet<28, [Q4_0, Q4_1, Q4_2, Q4_3], [Q3, Q7, Q11, Q15]>;
-
-// Q2 sub-registers of Q4 registers.
-def : SubRegSet<29, [Q4_0, Q4_1, Q4_2, Q4_3], [Q2_0, Q2_2, Q2_4, Q2_6]>;
-def : SubRegSet<30, [Q4_0, Q4_1, Q4_2, Q4_3], [Q2_1, Q2_3, Q2_5, Q2_7]>;
projects / oota-llvm.git / blobdiff