ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.

[oota-llvm.git] / lib / Target / ARM / ARMSchedule.td

diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td
index 7eb5ff665a6efe8bf17213ea59f6063df6655f8a..2d088de96e273d813b60680249c2a6b9e40d2b99 100644 (file)
--- a/lib/Target/ARM/ARMSchedule.td
+++ b/lib/Target/ARM/ARMSchedule.td
@@ -64,6 +64,11 @@ def WriteALUsr : SchedWrite; // Shift by register.
 def WriteALUSsr : SchedWrite; // Shift by register (flag setting).
 def ReadALUsr : SchedRead; // Some operands are read later.
 
+// Compares.
+def WriteCMP : SchedWrite;
+def WriteCMPsi : SchedWrite;
+def WriteCMPsr : SchedWrite;
+
 // Define TII for use in SchedVariant Predicates.
 def : PredicateProlog<[{
   const ARMBaseInstrInfo *TII =
@@ -71,6 +76,8 @@ def : PredicateProlog<[{
   (void)TII;
 }]>;
 
+def IsPredicatedPred : SchedPredicate<[{TII->isPredicated(MI)}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //