ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.

[oota-llvm.git] / lib / Target / ARM / ARMSchedule.td

diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td
index ff1ff2fccf0ffbd3d380d6eaf2b706811bd97dc4..2d088de96e273d813b60680249c2a6b9e40d2b99 100644 (file)
--- a/lib/Target/ARM/ARMSchedule.td
+++ b/lib/Target/ARM/ARMSchedule.td
@@ -56,13 +56,27 @@
 
 // Basic ALU operation.
 def WriteALU : SchedWrite;
-def ReadAdvanceALU : SchedRead;
+def ReadALU : SchedRead;
 
 // Basic ALU with shifts.
 def WriteALUsi : SchedWrite; // Shift by immediate.
 def WriteALUsr : SchedWrite; // Shift by register.
 def WriteALUSsr : SchedWrite; // Shift by register (flag setting).
-def ReadAdvanceALUsr : SchedRead; // Some operands are read later.
+def ReadALUsr : SchedRead; // Some operands are read later.
+
+// Compares.
+def WriteCMP : SchedWrite;
+def WriteCMPsi : SchedWrite;
+def WriteCMPsr : SchedWrite;
+
+// Define TII for use in SchedVariant Predicates.
+def : PredicateProlog<[{
+  const ARMBaseInstrInfo *TII =
+    static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
+  (void)TII;
+}]>;
+
+def IsPredicatedPred : SchedPredicate<[{TII->isPredicated(MI)}]>;
 
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM