// Basic ALU operation.
def WriteALU : SchedWrite;
-def ReadAdvanceALU : SchedRead;
+def ReadALU : SchedRead;
// Basic ALU with shifts.
def WriteALUsi : SchedWrite; // Shift by immediate.
def WriteALUsr : SchedWrite; // Shift by register.
def WriteALUSsr : SchedWrite; // Shift by register (flag setting).
-def ReadAdvanceALUsr : SchedRead; // Some operands are read later.
+def ReadALUsr : SchedRead; // Some operands are read later.
+
+// Compares.
+def WriteCMP : SchedWrite;
+def WriteCMPsi : SchedWrite;
+def WriteCMPsr : SchedWrite;
+
+// Division.
+def WriteDiv : SchedWrite;
+
+// Loads.
+def WriteLd : SchedWrite;
+def WritePreLd : SchedWrite;
+
+// Branches.
+def WriteBr : SchedWrite;
+def WriteBrL : SchedWrite;
+def WriteBrTbl : SchedWrite;
+
+// Fixpoint conversions.
+def WriteCvtFP : SchedWrite;
+
+// Noop.
+def WriteNoop : SchedWrite;
// Define TII for use in SchedVariant Predicates.
def : PredicateProlog<[{
(void)TII;
}]>;
+def IsPredicatedPred : SchedPredicate<[{TII->isPredicated(MI)}]>;
+
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for ARM
//