ARM "rrx" shift operands do not have an immediate. PR7790.

[oota-llvm.git] / lib / Target / ARM / ARMSchedule.td

diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td
index 1b8fc8bac874a778cd590c8882e67f41de5b2a6a..b60ccca46867aa10e7865735ab936c17229737ec 100644 (file)
--- a/lib/Target/ARM/ARMSchedule.td
+++ b/lib/Target/ARM/ARMSchedule.td
@@ -7,17 +7,6 @@
 // 
 //===----------------------------------------------------------------------===//
 
-//===----------------------------------------------------------------------===//
-// Functional units across ARM processors
-//
-def FU_Issue   : FuncUnit; // issue
-def FU_Pipe0   : FuncUnit; // pipeline 0
-def FU_Pipe1   : FuncUnit; // pipeline 1
-def FU_LdSt0   : FuncUnit; // pipeline 0 load/store
-def FU_LdSt1   : FuncUnit; // pipeline 1 load/store
-def FU_NPipe   : FuncUnit; // NEON ALU/MUL pipe
-def FU_NLSPipe : FuncUnit; // NEON LS pipe
-
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //
@@ -63,20 +52,22 @@ def IIC_iStoresiu  : InstrItinClass;
 def IIC_iStorem    : InstrItinClass;
 def IIC_Br         : InstrItinClass;
 def IIC_fpSTAT     : InstrItinClass;
-def IIC_fpMOVIS    : InstrItinClass;
-def IIC_fpMOVID    : InstrItinClass;
-def IIC_fpMOVSI    : InstrItinClass;
-def IIC_fpMOVDI    : InstrItinClass;
 def IIC_fpUNA32    : InstrItinClass;
 def IIC_fpUNA64    : InstrItinClass;
 def IIC_fpCMP32    : InstrItinClass;
 def IIC_fpCMP64    : InstrItinClass;
 def IIC_fpCVTSD    : InstrItinClass;
 def IIC_fpCVTDS    : InstrItinClass;
+def IIC_fpCVTSH    : InstrItinClass;
+def IIC_fpCVTHS    : InstrItinClass;
 def IIC_fpCVTIS    : InstrItinClass;
 def IIC_fpCVTID    : InstrItinClass;
 def IIC_fpCVTSI    : InstrItinClass;
 def IIC_fpCVTDI    : InstrItinClass;
+def IIC_fpMOVIS    : InstrItinClass;
+def IIC_fpMOVID    : InstrItinClass;
+def IIC_fpMOVSI    : InstrItinClass;
+def IIC_fpMOVDI    : InstrItinClass;
 def IIC_fpALU32    : InstrItinClass;
 def IIC_fpALU64    : InstrItinClass;
 def IIC_fpMUL32    : InstrItinClass;
@@ -102,11 +93,21 @@ def IIC_VUNAD      : InstrItinClass;
 def IIC_VUNAQ      : InstrItinClass;
 def IIC_VBIND      : InstrItinClass;
 def IIC_VBINQ      : InstrItinClass;
+def IIC_VMOVImm    : InstrItinClass;
 def IIC_VMOVD      : InstrItinClass;
 def IIC_VMOVQ      : InstrItinClass;
+def IIC_VMOVIS     : InstrItinClass;
+def IIC_VMOVID     : InstrItinClass;
+def IIC_VMOVISL    : InstrItinClass;
+def IIC_VMOVSI     : InstrItinClass;
+def IIC_VMOVDI     : InstrItinClass;
 def IIC_VPERMD     : InstrItinClass;
 def IIC_VPERMQ     : InstrItinClass;
 def IIC_VPERMQ3    : InstrItinClass;
+def IIC_VMACD      : InstrItinClass;
+def IIC_VMACQ      : InstrItinClass;
+def IIC_VRECSD     : InstrItinClass;
+def IIC_VRECSQ     : InstrItinClass;
 def IIC_VCNTiD     : InstrItinClass;
 def IIC_VCNTiQ     : InstrItinClass;
 def IIC_VUNAiD     : InstrItinClass;
@@ -119,99 +120,40 @@ def IIC_VSUBiD     : InstrItinClass;
 def IIC_VSUBiQ     : InstrItinClass;
 def IIC_VBINi4D    : InstrItinClass;
 def IIC_VBINi4Q    : InstrItinClass;
+def IIC_VSUBi4D    : InstrItinClass;
+def IIC_VSUBi4Q    : InstrItinClass;
+def IIC_VABAD      : InstrItinClass;
+def IIC_VABAQ      : InstrItinClass;
+def IIC_VSHLiD     : InstrItinClass;
+def IIC_VSHLiQ     : InstrItinClass;
+def IIC_VSHLi4D    : InstrItinClass;
+def IIC_VSHLi4Q    : InstrItinClass;
+def IIC_VPALiD     : InstrItinClass;
+def IIC_VPALiQ     : InstrItinClass;
 def IIC_VMULi16D   : InstrItinClass;
 def IIC_VMULi32D   : InstrItinClass;
 def IIC_VMULi16Q   : InstrItinClass;
 def IIC_VMULi32Q   : InstrItinClass;
+def IIC_VMACi16D   : InstrItinClass;
+def IIC_VMACi32D   : InstrItinClass;
+def IIC_VMACi16Q   : InstrItinClass;
+def IIC_VMACi32Q   : InstrItinClass;
+def IIC_VEXTD      : InstrItinClass;
+def IIC_VEXTQ      : InstrItinClass;
+def IIC_VTB1       : InstrItinClass;
+def IIC_VTB2       : InstrItinClass;
+def IIC_VTB3       : InstrItinClass;
+def IIC_VTB4       : InstrItinClass;
+def IIC_VTBX1      : InstrItinClass;
+def IIC_VTBX2      : InstrItinClass;
+def IIC_VTBX3      : InstrItinClass;
+def IIC_VTBX4      : InstrItinClass;
 
 //===----------------------------------------------------------------------===//
 // Processor instruction itineraries.
 
-def GenericItineraries : ProcessorItineraries<[
-  InstrItinData<IIC_iALUx   , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iALUi   , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iALUr   , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iALUsi  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iALUsr  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iUNAr   , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iUNAsi  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iUNAsr  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iCMPi   , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iCMPr   , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iCMPsi  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iCMPsr  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iMOVi   , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iMOVr   , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iMOVsi  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iMOVsr  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iCMOVi  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iCMOVr  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iMUL16  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iMAC16  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iMUL32  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iMAC32  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iMUL64  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iMAC64  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iLoadi  , [InstrStage<1, [FU_Pipe0]>,
-                               InstrStage<1, [FU_LdSt0]>]>,
-  InstrItinData<IIC_iLoadr  , [InstrStage<1, [FU_Pipe0]>,
-                               InstrStage<1, [FU_LdSt0]>]>,
-  InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
-                               InstrStage<1, [FU_LdSt0]>]>,
-  InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
-                               InstrStage<1, [FU_LdSt0]>]>,
-  InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
-                               InstrStage<1, [FU_LdSt0]>]>,
-  InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
-                               InstrStage<1, [FU_LdSt0]>]>,
-  InstrItinData<IIC_iLoadm  , [InstrStage<2, [FU_Pipe0]>,
-                               InstrStage<2, [FU_LdSt0]>]>,
-  InstrItinData<IIC_iStorei  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iStorer  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_iStorem  , [InstrStage<2, [FU_Pipe0]>]>,
-  InstrItinData<IIC_Br       , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpSTAT   , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpMOVSI  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpMOVDI  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpMOVIS  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpMOVID  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpUNA32  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpUNA64  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpCMP32  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpCMP64  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpCVTSD  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpCVTDS  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpCVTIS  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpCVTID  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpCVTSI  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpCVTDI  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpALU32  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpALU64  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpMUL32  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpMUL64  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpMAC32  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpMAC64  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpDIV32  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpDIV64  , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpSQRT32 , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpSQRT64 , [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpLoad32 , [InstrStage<1, [FU_Pipe0]>,
-                                InstrStage<1, [FU_LdSt0]>]>,
-  InstrItinData<IIC_fpLoad64 , [InstrStage<1, [FU_Pipe0]>,
-                                InstrStage<1, [FU_LdSt0]>]>,
-  InstrItinData<IIC_fpLoadm  , [InstrStage<1, [FU_Pipe0]>,
-                                InstrStage<1, [FU_LdSt0]>]>,
-  InstrItinData<IIC_fpStore32, [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpStore64, [InstrStage<1, [FU_Pipe0]>]>,
-  InstrItinData<IIC_fpStorem , [InstrStage<1, [FU_Pipe0]>]>
-]>;
-
+def GenericItineraries : ProcessorItineraries<[], []>;
 
 include "ARMScheduleV6.td"
-include "ARMScheduleV7.td"
+include "ARMScheduleA8.td"
+include "ARMScheduleA9.td"