// Swift machine model for scheduling and other instruction cost heuristics.
def SwiftModel : SchedMachineModel {
let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
- let MinLatency = 0; // Data dependencies are allowed within dispatch groups.
+ let MicroOpBufferSize = 45; // Based on NEON renamed registers.
let LoadLatency = 3;
let MispredictPenalty = 14; // A branch direction mispredict.
}
// 4.2.18 Integer Divide
def : WriteRes<WriteDiv, [SwiftUnitDiv]>; // Workaround.
- def : InstRW < [WriteDiv],
+ def : InstRW <[SwiftDiv],
(instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>;
// 4.2.19 Integer Load Single Element