Nuke the old JIT.

[oota-llvm.git] / lib / Target / ARM / ARMSubtarget.cpp

diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp
index ea9e2b84c196133a3d62e1349090088c18dcc178..2ce083ca2b624af1311a7263ca507245a6fdb950 100644 (file)
--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -15,7 +15,6 @@
 #include "ARMFrameLowering.h"
 #include "ARMISelLowering.h"
 #include "ARMInstrInfo.h"
-#include "ARMJITInfo.h"
 #include "ARMSelectionDAGInfo.h"
 #include "ARMSubtarget.h"
 #include "ARMMachineFunctionInfo.h"
@@ -158,7 +157,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
       ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
       TargetTriple(TT), Options(Options), TargetABI(ARM_ABI_UNKNOWN),
       DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
-      TSInfo(DL), JITInfo(),
+      TSInfo(DL),
       InstrInfo(isThumb1Only()
                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
                     : !isThumb()
@@ -438,51 +437,3 @@ bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
                      !MF.getFunction()->getAttributes().hasAttribute(
                          AttributeSet::FunctionIndex, Attribute::MinSize));
 }
-
-bool ARMSubtarget::shouldCoalesce(MachineInstr *MI,
-                                  const TargetRegisterClass *SrcRC,
-                                  unsigned SubReg,
-                                  const TargetRegisterClass *DstRC,
-                                  unsigned DstSubReg,
-                                  const TargetRegisterClass *NewRC) const {
-  auto MBB = MI->getParent();
-  auto MF = MBB->getParent();
-  const MachineRegisterInfo &MRI = MF->getRegInfo();
-  // If not copying into a sub-register this should be ok because we shouldn't
-  // need to split the reg.
-  if (!DstSubReg)
-    return true;
-  // Small registers don't frequently cause a problem, so we can coalesce them.
-  if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
-    return true;
-
-  auto NewRCWeight =
-              MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC);
-  auto SrcRCWeight =
-              MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
-  auto DstRCWeight =
-              MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
-  // If the source register class is more expensive than the destination, the
-  // coalescing is probably profitable.
-  if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
-    return true;
-  if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
-    return true;
-
-  // If the register allocator isn't constrained, we can always allow coalescing
-  // unfortunately we don't know yet if we will be constrained.
-  // The goal of this heuristic is to restrict how many expensive registers
-  // we allow to coalesce in a given basic block.
-  auto AFI = MF->getInfo<ARMFunctionInfo>();
-  auto It = AFI->getCoalescedWeight(MBB);
-
-  DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: " << It->second << "\n");
-  DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: " << NewRCWeight.RegWeight << "\n");
-  unsigned SizeMultiplier = MBB->size()/100;
-  SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
-  if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
-    It->second += NewRCWeight.RegWeight;
-    return true;
-  }
-  return false;
-}