ARM: constrain Thumb LDRLIT pseudo-instructions to r0-r7.

[oota-llvm.git] / lib / Target / ARM / ARMTargetMachine.cpp

diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index 1d60e5de559ffc4b943c1e6bd1e177bfc186cd33..718311ba1decc483d6f106c7af620db934d2629b 100644 (file)
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -51,7 +51,8 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
     Subtarget(TT, CPU, FS, Options),
     JITInfo(),
     InstrItins(Subtarget.getInstrItineraryData()) {
-  // Default to soft float ABI
+
+  // Default to triple-appropriate float ABI
   if (Options.FloatABIType == FloatABI::Default)
     this->Options.FloatABIType =
         Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
@@ -69,8 +70,13 @@ void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
 void ARMTargetMachine::anchor() { }
 
 static std::string computeDataLayout(ARMSubtarget &ST) {
-  // Little endian. Pointers are 32 bits and aligned to 32 bits.
-  std::string Ret = "e-p:32:32";
+  // Little endian.
+  std::string Ret = "e";
+
+  Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
+
+  // Pointers are 32 bits and aligned to 32 bits.
+  Ret += "-p:32:32";
 
   // On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
   // align to 32.
@@ -101,8 +107,11 @@ static std::string computeDataLayout(ARMSubtarget &ST) {
   // Integer registers are 32 bits.
   Ret += "-n32";
 
-  // The stack is 64 bit aligned on AAPCS and 32 bit aligned everywhere else.
-  if (ST.isAAPCS_ABI())
+  // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
+  // aligned everywhere else.
+  if (ST.isTargetNaCl())
+    Ret += "-S128";
+  else if (ST.isAAPCS_ABI())
     Ret += "-S64";
   else
     Ret += "-S32";