The BLX instruction is encoded differently than the BL, because why not? In

[oota-llvm.git] / lib / Target / ARM / ARMTargetMachine.cpp

diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index 9aa7c1f16adec641e0d9a210ec3600affe3ad4bc..89047f4051f9588cd5e5f572aedb6871f69c3470 100644 (file)
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -16,11 +16,14 @@
 #include "ARM.h"
 #include "llvm/PassManager.h"
 #include "llvm/CodeGen/Passes.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetRegistry.h"
 using namespace llvm;
 
+static cl::opt<bool>ExpandMLx("expand-fp-mlx", cl::init(false), cl::Hidden);
+
 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
   Triple TheTriple(TT);
   switch (TheTriple.getOS()) {
@@ -34,13 +37,12 @@ static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
 // This is duplicated code. Refactor this.
 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
                                     MCContext &Ctx, TargetAsmBackend &TAB,
-                                    raw_ostream &_OS,
-                                    MCCodeEmitter *_Emitter,
+                                    raw_ostream &OS,
+                                    MCCodeEmitter *Emitter,
                                     bool RelaxAll) {
-  Triple TheTriple(TT);
-  switch (TheTriple.getOS()) {
+  switch (Triple(TT).getOS()) {
   case Triple::Darwin:
-    return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
+    return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
   case Triple::MinGW32:
   case Triple::MinGW64:
   case Triple::Cygwin:
@@ -48,7 +50,7 @@ static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
     llvm_unreachable("ARM does not support Windows COFF format");
     return NULL;
   default:
-    return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
+    return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
   }
 }
 
@@ -62,22 +64,16 @@ extern "C" void LLVMInitializeARMTarget() {
   RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
 
   // Register the MC Code Emitter
-  TargetRegistry::RegisterCodeEmitter(TheARMTarget,
-                                      createARMMCCodeEmitter);
-  TargetRegistry::RegisterCodeEmitter(TheThumbTarget,
-                                      createARMMCCodeEmitter);
+  TargetRegistry::RegisterCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
+  TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
 
   // Register the asm backend.
-  TargetRegistry::RegisterAsmBackend(TheARMTarget,
-                                     createARMAsmBackend);
-  TargetRegistry::RegisterAsmBackend(TheThumbTarget,
-                                     createARMAsmBackend);
+  TargetRegistry::RegisterAsmBackend(TheARMTarget, createARMAsmBackend);
+  TargetRegistry::RegisterAsmBackend(TheThumbTarget, createARMAsmBackend);
 
   // Register the object streamer.
-  TargetRegistry::RegisterObjectStreamer(TheARMTarget,
-                                         createMCStreamer);
-  TargetRegistry::RegisterObjectStreamer(TheThumbTarget,
-                                         createMCStreamer);
+  TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer);
+  TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer);
 
 }
 
@@ -153,6 +149,9 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
   if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
     PM.add(createARMLoadStoreOptimizationPass(true));
+  if (ExpandMLx &&
+      OptLevel != CodeGenOpt::None && Subtarget.hasVFP2())
+    PM.add(createMLxExpansionPass());
 
   return true;
 }