Fix some remaining issues with decoding ARM-mode memory instructions, and add another...

[oota-llvm.git] / lib / Target / ARM / Disassembler / ARMDisassembler.cpp

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 7de0c236ac1efcfa20c6405d45b0a9c7fc9e689e..5cebabc65b25cca77896fda3f52b11d7996b83da 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -129,8 +129,6 @@ static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn,
-                               uint64_t Address, const void *Decoder);
 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
@@ -970,6 +968,7 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
     case ARM::LDRB_POST_IMM:
     case ARM::LDRB_POST_REG:
     case ARM::LDR_PRE:
+    case ARM::LDRB_PRE:
     case ARM::LDRBT_POST_REG:
     case ARM::LDRBT_POST_IMM:
     case ARM::LDRT_POST_REG:
@@ -1090,6 +1089,9 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
     case ARM::STRD:
     case ARM::STRD_PRE:
     case ARM::STRD_POST:
+    case ARM::STRH:
+    case ARM::STRH_PRE:
+    case ARM::STRH_POST:
       if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
         return false;
       break;
@@ -1120,6 +1122,15 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
     case ARM::LDRD:
     case ARM::LDRD_PRE:
     case ARM::LDRD_POST:
+    case ARM::LDRH:
+    case ARM::LDRH_PRE:
+    case ARM::LDRH_POST:
+    case ARM::LDRSH:
+    case ARM::LDRSH_PRE:
+    case ARM::LDRSH_POST:
+    case ARM::LDRSB:
+    case ARM::LDRSB_PRE:
+    case ARM::LDRSB_POST:
     case ARM::LDRHTr:
     case ARM::LDRSBTr:
       if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
@@ -2448,23 +2459,6 @@ static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
   return true;
 }
 
-static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val,
-                                  uint64_t Address, const void *Decoder) {
-  bool isImm = fieldFromInstruction32(Val, 9, 1);
-  bool isAdd = fieldFromInstruction32(Val, 8, 1);
-  unsigned imm = fieldFromInstruction32(Val, 0, 8);
-
-  if (!isImm) {
-    if (!DecodeGPRRegisterClass(Inst, imm, Address, Decoder)) return false;
-    Inst.addOperand(MCOperand::CreateImm(!isAdd << 8));
-  } else {
-    Inst.addOperand(MCOperand::CreateReg(0));
-    Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8)));
-  }
-
-  return true;
-}
-
 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
                                    uint64_t Address, const void *Decoder) {
   switch (Val) {