return;
}
- if (Opcode == ARM::tLDMIA || Opcode == ARM::tSTMIA) {
+ if (Opcode == ARM::tLDMIA) {
bool Writeback = true;
unsigned BaseReg = MI->getOperand(0).getReg();
for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
Writeback = false;
}
- if (Opcode == ARM::tLDMIA)
- O << "\tldmia";
- else if (Opcode == ARM::tSTMIA)
- O << "\tstmia";
- else
- llvm_unreachable("Unknown opcode!");
+ O << "\tldm";
printPredicateOperand(MI, 1, O);
O << '\t' << getRegisterName(BaseReg);
return;
}
+ // Thumb1 NOP
+ if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
+ MI->getOperand(1).getReg() == ARM::R8) {
+ O << "\tnop";
+ printPredicateOperand(MI, 2, O);
+ return;
+ }
+
printInstruction(MI, O);
}
O << "[" << getRegisterName(MO1.getReg());
- if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
+ unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
+ unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
+ if (ImmOffs || Op == ARM_AM::sub) {
O << ", #"
<< ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
<< ImmOffs * 4;
O << ", ror #";
switch (Imm) {
default: assert (0 && "illegal ror immediate!");
- case 1: O << "8\n"; break;
- case 2: O << "16\n"; break;
- case 3: O << "24\n"; break;
+ case 1: O << "8"; break;
+ case 2: O << "16"; break;
+ case 3: O << "24"; break;
}
}