private:
const TargetRegisterInfo *TRI;
const ARMBaseInstrInfo *TII;
- const ARMSubtarget *Subtarget;
typedef DenseMap<unsigned, const MachineInstr*> RegMap;
MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
MachineBasicBlock::iterator NextMII;
for (; MII != E; MII = NextMII) {
- NextMII = next(MII);
+ NextMII = llvm::next(MII);
MachineInstr *MI = &*MII;
- if (MI->getOpcode() == ARM::FCPYD &&
+ if (MI->getOpcode() == ARM::VMOVD &&
!TII->isPredicated(MI)) {
unsigned SrcReg = MI->getOperand(1).getReg();
- // If we do not found an instruction defining the reg, this means the
+ // If we do not find an instruction defining the reg, this means the
// register should be live-in for this BB. It's always to better to use
// NEON reg-reg moves.
unsigned Domain = ARMII::DomainNEON;
Domain = ARMII::DomainNEON;
}
- if ((Domain & ARMII::DomainNEON) && Subtarget->hasNEON()) {
- // Convert FCPYD to VMOVD.
+ if (Domain & ARMII::DomainNEON) {
+ // Convert VMOVD to VMOVDneon
unsigned DestReg = MI->getOperand(0).getReg();
DEBUG({errs() << "vmov convert: "; MI->dump();});
// afterwards
// - The imp-defs / imp-uses are superregs only, we don't care about
// them.
- BuildMI(MBB, *MI, MI->getDebugLoc(),
- TII->get(ARM::VMOVD), DestReg).addReg(SrcReg);
+ AddDefaultPred(BuildMI(MBB, *MI, MI->getDebugLoc(),
+ TII->get(ARM::VMOVDneon), DestReg).addReg(SrcReg));
MBB.erase(MI);
MachineBasicBlock::iterator I = prior(NextMII);
MI = &*I;
Modified = true;
++NumVMovs;
} else {
- assert((Domain & ARMII::DomainVFP ||
- !Subtarget->hasNEON()) && "Invalid domain!");
+ assert((Domain & ARMII::DomainVFP) && "Invalid domain!");
// Do nothing.
}
}
return false;
TRI = TM.getRegisterInfo();
- Subtarget = &TM.getSubtarget<ARMSubtarget>();
TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
bool Modified = false;