Do not generate 32-bit call on win64 when imm does not fit

[oota-llvm.git] / lib / Target / ARM / README.txt

diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt
index a587a2bf7ea32cf70a88a5683f3b2dc114a2ae60..08435c57ebb6803121141213a652965bc6483249 100644 (file)
--- a/lib/Target/ARM/README.txt
+++ b/lib/Target/ARM/README.txt
@@ -546,3 +546,49 @@ We need to fix constant isel for ARMv6t2 to use MOVT.
 
 Constant island pass should make use of full range SoImm values for LEApcrel.
 Be careful though as the last attempt caused infinite looping on lencod.
+
+//===---------------------------------------------------------------------===//
+
+Predication issue. This function:   
+
+extern unsigned array[ 128 ];
+int     foo( int x ) {
+  int     y;
+  y = array[ x & 127 ];
+  if ( x & 128 )
+     y = 123456789 & ( y >> 2 );
+  else
+     y = 123456789 & y;
+  return y;
+}
+
+compiles to:
+
+_foo:
+       and r1, r0, #127
+       ldr r2, LCPI1_0
+       ldr r2, [r2]
+       ldr r1, [r2, +r1, lsl #2]
+       mov r2, r1, lsr #2
+       tst r0, #128
+       moveq r2, r1
+       ldr r0, LCPI1_1
+       and r0, r2, r0
+       bx lr
+
+It would be better to do something like this, to fold the shift into the
+conditional move:
+
+       and r1, r0, #127
+       ldr r2, LCPI1_0
+       ldr r2, [r2]
+       ldr r1, [r2, +r1, lsl #2]
+       tst r0, #128
+       movne r1, r1, lsr #2
+       ldr r0, LCPI1_1
+       and r0, r1, r0
+       bx lr
+
+it saves an instruction and a register.
+
+//===---------------------------------------------------------------------===//