ARM "rrx" shift operands do not have an immediate. PR7790.

[oota-llvm.git] / lib / Target / ARM / README.txt

diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt
index 85d5ca05913cb6b05b743beb66b483005dee3707..9fc3fb92cb2c1c4a7a7fc5062d1cfe5c590a8885 100644 (file)
--- a/lib/Target/ARM/README.txt
+++ b/lib/Target/ARM/README.txt
@@ -590,3 +590,70 @@ than the Z bit, we'll need additional logic to reverse the conditionals
 associated with the comparison. Perhaps a pseudo-instruction for the comparison,
 with a post-codegen pass to clean up and handle the condition codes?
 See PR5694 for testcase.
+
+//===---------------------------------------------------------------------===//
+
+Given the following on armv5:
+int test1(int A, int B) {
+  return (A&-8388481)|(B&8388480);
+}
+
+We currently generate:
+       ldr     r2, .LCPI0_0
+       and     r0, r0, r2
+       ldr     r2, .LCPI0_1
+       and     r1, r1, r2
+       orr     r0, r1, r0
+       bx      lr
+
+We should be able to replace the second ldr+and with a bic (i.e. reuse the
+constant which was already loaded).  Not sure what's necessary to do that.
+
+//===---------------------------------------------------------------------===//
+
+The code generated for bswap on armv4/5 (CPUs without rev) is less than ideal:
+
+int a(int x) { return __builtin_bswap32(x); }
+
+a:
+       mov     r1, #255, 24
+       mov     r2, #255, 16
+       and     r1, r1, r0, lsr #8
+       and     r2, r2, r0, lsl #8
+       orr     r1, r1, r0, lsr #24
+       orr     r0, r2, r0, lsl #24
+       orr     r0, r0, r1
+       bx      lr
+
+Something like the following would be better (fewer instructions/registers):
+       eor     r1, r0, r0, ror #16
+       bic     r1, r1, #0xff0000
+       mov     r1, r1, lsr #8
+       eor     r0, r1, r0, ror #8
+       bx      lr
+
+A custom Thumb version would also be a slight improvement over the generic
+version.
+
+//===---------------------------------------------------------------------===//
+
+Consider the following simple C code:
+
+void foo(unsigned char *a, unsigned char *b, int *c) {
+ if ((*a | *b) == 0) *c = 0;
+}
+
+currently llvm-gcc generates something like this (nice branchless code I'd say):
+
+       ldrb    r0, [r0]
+       ldrb    r1, [r1]
+       orr     r0, r1, r0
+       tst     r0, #255
+       moveq   r0, #0
+       streq   r0, [r2]
+       bx      lr
+
+Note that both "tst" and "moveq" are redundant.
+
+//===---------------------------------------------------------------------===//
+