-//===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------*- C++ -*-===//
+//===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
-#include "ARMInstrInfo.h"
+#include "Thumb2InstrInfo.h"
#include "ARM.h"
+#include "ARMConstantPoolValue.h"
#include "ARMAddressingModes.h"
#include "ARMGenInstrInfo.inc"
#include "ARMMachineFunctionInfo.h"
using namespace llvm;
-Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI) : RI(*this, STI) {
+Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
+ : ARMBaseInstrInfo(STI), RI(*this, STI) {
}
unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
return 0;
}
-bool
-Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
- if (MBB.empty()) return false;
-
- switch (MBB.back().getOpcode()) {
- case ARM::t2LDM_RET:
- case ARM::t2B: // Uncond branch.
- case ARM::t2BR_JT: // Jumptable branch.
- case ARM::t2TBB: // Table branch byte.
- case ARM::t2TBH: // Table branch halfword.
- case ARM::tBR_JTr: // Jumptable branch (16-bit version).
- case ARM::tBX_RET:
- case ARM::tBX_RET_vararg:
- case ARM::tPOP_RET:
- case ARM::tB:
- case ARM::tBRIND:
- return true;
- default:
- break;
- }
-
- return false;
-}
-
bool
Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC);
}
-
void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI, DebugLoc dl,
unsigned DestReg, unsigned BaseReg, int NumBytes,
Offset += MI.getOperand(FrameRegIdx+1).getImm();
bool isSP = FrameReg == ARM::SP;
- if (Offset == 0) {
+ unsigned PredReg;
+ if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
// Turn it into a move.
MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
- MI.RemoveOperand(FrameRegIdx+1);
- Offset = 0;
+ // Remove offset and remaining explicit predicate operands.
+ do MI.RemoveOperand(FrameRegIdx+1);
+ while (MI.getNumOperands() > FrameRegIdx+1 &&
+ (!MI.getOperand(FrameRegIdx+1).isReg() ||
+ !MI.getOperand(FrameRegIdx+1).isImm()));
return true;
}
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
} else {
- // AddrMode4 cannot handle any offset.
- if (AddrMode == ARMII::AddrMode4)
+ // AddrMode4 and AddrMode6 cannot handle any offset.
+ if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
return false;
// AddrModeT2_so cannot handle any offset. If there is no offset
NewOpc = positiveOffsetOpcode(Opcode);
NumBits = 12;
}
- } else {
- // VFP and NEON address modes.
- int InstrOffs = 0;
- if (AddrMode == ARMII::AddrMode5) {
- const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
- InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
- if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
- InstrOffs *= -1;
- }
+ } else if (AddrMode == ARMII::AddrMode5) {
+ // VFP address mode.
+ const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
+ int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
+ if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
+ InstrOffs *= -1;
NumBits = 8;
Scale = 4;
Offset += InstrOffs * 4;
Offset = -Offset;
isSub = true;
}
+ } else {
+ llvm_unreachable("Unsupported addressing mode!");
}
if (NewOpc != Opcode)