AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.

[oota-llvm.git] / lib / Target / ARM64 / ARM64DeadRegisterDefinitionsPass.cpp

diff --git a/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp b/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
index f85dbaa806ffa360ac0c1b450f4adaeb9a464971..e8f03ec833f7014f3c270907004749446af1d0ad 100644 (file)
--- a/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
+++ b/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
@@ -11,7 +11,6 @@
 // hardware's register renamer.
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "arm64-dead-defs"
 #include "ARM64.h"
 #include "ARM64RegisterInfo.h"
 #include "llvm/ADT/Statistic.h"
@@ -22,24 +21,26 @@
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
+#define DEBUG_TYPE "arm64-dead-defs"
+
 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
 
 namespace {
 class ARM64DeadRegisterDefinitions : public MachineFunctionPass {
 private:
   const TargetRegisterInfo *TRI;
-  bool implicitlyDefinesSubReg(unsigned Reg, const MachineInstr *MI);
-  bool processMachineBasicBlock(MachineBasicBlock *MBB);
-
+  bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI);
+  bool processMachineBasicBlock(MachineBasicBlock &MBB);
+  bool usesFrameIndex(const MachineInstr &MI);
 public:
   static char ID; // Pass identification, replacement for typeid.
   explicit ARM64DeadRegisterDefinitions() : MachineFunctionPass(ID) {}
 
-  virtual bool runOnMachineFunction(MachineFunction &F);
+  virtual bool runOnMachineFunction(MachineFunction &F) override;
 
-  const char *getPassName() const { return "Dead register definitions"; }
+  const char *getPassName() const override { return "Dead register definitions"; }
 
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+  virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
@@ -47,45 +48,54 @@ public:
 char ARM64DeadRegisterDefinitions::ID = 0;
 } // end anonymous namespace
 
-bool ARM64DeadRegisterDefinitions::implicitlyDefinesSubReg(
-                                                       unsigned Reg,
-                                                       const MachineInstr *MI) {
-  for (unsigned i = MI->getNumExplicitOperands(), e = MI->getNumOperands();
-       i != e; ++i) {
-    const MachineOperand &MO = MI->getOperand(i);
+bool ARM64DeadRegisterDefinitions::implicitlyDefinesOverlappingReg(
+    unsigned Reg, const MachineInstr &MI) {
+  for (const MachineOperand &MO : MI.implicit_operands())
     if (MO.isReg() && MO.isDef())
-      if (TRI->isSubRegister(Reg, MO.getReg()))
+      if (TRI->regsOverlap(Reg, MO.getReg()))
         return true;
-  }
+  return false;
+}
+
+bool ARM64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr &MI) {
+  for (const MachineOperand &Op : MI.uses())
+    if (Op.isFI())
+      return true;
   return false;
 }
 
 bool
-ARM64DeadRegisterDefinitions::processMachineBasicBlock(MachineBasicBlock *MBB) {
+ARM64DeadRegisterDefinitions::processMachineBasicBlock(MachineBasicBlock &MBB) {
   bool Changed = false;
-  for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
-       ++I) {
-    MachineInstr *MI = I;
-    for (int i = 0, e = MI->getDesc().getNumDefs(); i != e; ++i) {
-      MachineOperand &MO = MI->getOperand(i);
+  for (MachineInstr &MI : MBB) {
+    if (usesFrameIndex(MI)) {
+      // We need to skip this instruction because while it appears to have a
+      // dead def it uses a frame index which might expand into a multi
+      // instruction sequence during EPI.
+      DEBUG(dbgs() << "    Ignoring, operand is frame index\n");
+      continue;
+    }
+    for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
+      MachineOperand &MO = MI.getOperand(i);
       if (MO.isReg() && MO.isDead() && MO.isDef()) {
         assert(!MO.isImplicit() && "Unexpected implicit def!");
         DEBUG(dbgs() << "  Dead def operand #" << i << " in:\n    ";
-              MI->print(dbgs()));
+              MI.print(dbgs()));
         // Be careful not to change the register if it's a tied operand.
-        if (MI->isRegTiedToUseOperand(i)) {
+        if (MI.isRegTiedToUseOperand(i)) {
           DEBUG(dbgs() << "    Ignoring, def is tied operand.\n");
           continue;
         }
-        // Don't change the register if there's an implicit def of a subreg.
-        if (implicitlyDefinesSubReg(MO.getReg(), MI)) {
-          DEBUG(dbgs() << "    Ignoring, implicitly defines subregister.\n");
+        // Don't change the register if there's an implicit def of a subreg or
+        // supperreg.
+        if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) {
+          DEBUG(dbgs() << "    Ignoring, implicitly defines overlap reg.\n");
           continue;
         }
         // Make sure the instruction take a register class that contains
         // the zero register and replace it if so.
         unsigned NewReg;
-        switch (MI->getDesc().OpInfo[i].RegClass) {
+        switch (MI.getDesc().OpInfo[i].RegClass) {
         default:
           DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
           continue;
@@ -98,7 +108,7 @@ ARM64DeadRegisterDefinitions::processMachineBasicBlock(MachineBasicBlock *MBB) {
         }
         DEBUG(dbgs() << "    Replacing with zero register. New:\n      ");
         MO.setReg(NewReg);
-        DEBUG(MI->print(dbgs()));
+        DEBUG(MI.print(dbgs()));
         ++NumDeadDefsReplaced;
       }
     }
@@ -108,14 +118,13 @@ ARM64DeadRegisterDefinitions::processMachineBasicBlock(MachineBasicBlock *MBB) {
 
 // Scan the function for instructions that have a dead definition of a
 // register. Replace that register with the zero register when possible.
-bool ARM64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &mf) {
-  MachineFunction *MF = &mf;
-  TRI = MF->getTarget().getRegisterInfo();
+bool ARM64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
+  TRI = MF.getTarget().getRegisterInfo();
   bool Changed = false;
   DEBUG(dbgs() << "***** ARM64DeadRegisterDefinitions *****\n");
 
-  for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I)
-    if (processMachineBasicBlock(I))
+  for (auto &MBB : MF)
+    if (processMachineBasicBlock(MBB))
       Changed = true;
   return Changed;
 }