Undo a change made in r140254.

[oota-llvm.git] / lib / Target / Alpha / Alpha.td

diff --git a/lib/Target/Alpha/Alpha.td b/lib/Target/Alpha/Alpha.td
index 39c185b47ba47d99f1f1a5e9de35c8778065a395..ae79c2e4b70ec7ed6d40f41056132e62c75da007 100644 (file)
--- a/lib/Target/Alpha/Alpha.td
+++ b/lib/Target/Alpha/Alpha.td
@@ -2,8 +2,8 @@
 // 
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
 //
@@ -12,7 +12,7 @@
 
 // Get the target-independent interfaces which we are implementing...
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //Alpha is little endian
 
@@ -20,10 +20,8 @@ include "../Target.td"
 // Subtarget Features
 //===----------------------------------------------------------------------===//
 
-def FeatureCIX : SubtargetFeature<"CIX", "HasCT", "true",
-                                  "Enable CIX extentions">;
-def FeatureFIX : SubtargetFeature<"FIX", "HasF2I", "true",
-                                  "Enable FIX extentions">;
+def FeatureCIX : SubtargetFeature<"cix", "HasCT", "true",
+                                  "Enable CIX extensions">;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
@@ -31,6 +29,12 @@ def FeatureFIX : SubtargetFeature<"FIX", "HasF2I", "true",
 
 include "AlphaRegisterInfo.td"
 
+//===----------------------------------------------------------------------===//
+// Calling Convention Description
+//===----------------------------------------------------------------------===//
+
+include "AlphaCallingConv.td"
+
 //===----------------------------------------------------------------------===//
 // Schedule Description
 //===----------------------------------------------------------------------===//
@@ -43,21 +47,15 @@ include "AlphaSchedule.td"
 
 include "AlphaInstrInfo.td"
 
-def AlphaInstrInfo : InstrInfo {
-  // Define how we want to layout our target-specific information field.
- // let TSFlagsFields = [];
- // let TSFlagsShifts = [];
-}
+def AlphaInstrInfo : InstrInfo;
 
 //===----------------------------------------------------------------------===//
 // Alpha Processor Definitions
 //===----------------------------------------------------------------------===//
 
 def : Processor<"generic", Alpha21264Itineraries, []>;
-def : Processor<"pca56"  , Alpha21264Itineraries, []>;
-def : Processor<"ev56"   , Alpha21264Itineraries, []>;
-def : Processor<"ev6"    , Alpha21264Itineraries, [FeatureFIX]>;
-def : Processor<"ev67"   , Alpha21264Itineraries, [FeatureFIX, FeatureCIX]>;
+def : Processor<"ev6"    , Alpha21264Itineraries, []>;
+def : Processor<"ev67"   , Alpha21264Itineraries, [FeatureCIX]>;
 
 //===----------------------------------------------------------------------===//
 // The Alpha Target