convert this to filecheck style and make it a test of darwin/PPC's

[oota-llvm.git] / lib / Target / Alpha / Alpha.td

diff --git a/lib/Target/Alpha/Alpha.td b/lib/Target/Alpha/Alpha.td
index e48bea1e205080eb6634baacbeaa0052bc7d8605..e3748c6a09f397da712f25fdf53ce2dced8fdc9d 100644 (file)
--- a/lib/Target/Alpha/Alpha.td
+++ b/lib/Target/Alpha/Alpha.td
@@ -1,9 +1,9 @@
-//===- Alpha.td - Describe the Alpha Target Machine ----*- tablegen -*-===//
+//===- Alpha.td - Describe the Alpha Target Machine --------*- tablegen -*-===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
 //
@@ -12,16 +12,29 @@
 
 // Get the target-independent interfaces which we are implementing...
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //Alpha is little endian
 
+//===----------------------------------------------------------------------===//
+// Subtarget Features
+//===----------------------------------------------------------------------===//
+
+def FeatureCIX : SubtargetFeature<"cix", "HasCT", "true",
+                                  "Enable CIX extentions">;
+
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "AlphaRegisterInfo.td"
 
+//===----------------------------------------------------------------------===//
+// Schedule Description
+//===----------------------------------------------------------------------===//
+
+include "AlphaSchedule.td"
+
 //===----------------------------------------------------------------------===//
 // Instruction Descriptions
 //===----------------------------------------------------------------------===//
@@ -29,28 +42,25 @@ include "AlphaRegisterInfo.td"
 include "AlphaInstrInfo.td"
 
 def AlphaInstrInfo : InstrInfo {
-  let PHIInst = PHI;
-
   // Define how we want to layout our target-specific information field.
  // let TSFlagsFields = [];
  // let TSFlagsShifts = [];
 }
 
-def Alpha : Target {
-  // Pointers on Alpha are 64-bits in size.
-  let PointerType = i64;
-
-  let CalleeSavedRegisters = 
-       //saved regs
-       [R9, R10, R11, R12, R13, R14, 
-       //Frame pointer
-       R15, 
-       //return address
-       R26, 
-       //Stack Pointer
-       R30,
-         F2, F3, F4, F5, F6, F7, F8, F9];
+//===----------------------------------------------------------------------===//
+// Alpha Processor Definitions
+//===----------------------------------------------------------------------===//
 
+def : Processor<"generic", Alpha21264Itineraries, []>;
+def : Processor<"ev6"    , Alpha21264Itineraries, []>;
+def : Processor<"ev67"   , Alpha21264Itineraries, [FeatureCIX]>;
+
+//===----------------------------------------------------------------------===//
+// The Alpha Target
+//===----------------------------------------------------------------------===//
+
+
+def Alpha : Target {
   // Pull in Instruction Info:
   let InstructionSet = AlphaInstrInfo;
 }