convert this to filecheck style and make it a test of darwin/PPC's

[oota-llvm.git] / lib / Target / Alpha / Alpha.td

diff --git a/lib/Target/Alpha/Alpha.td b/lib/Target/Alpha/Alpha.td
index facc767c40b636284800f1d20b63b203006e1423..e3748c6a09f397da712f25fdf53ce2dced8fdc9d 100644 (file)
--- a/lib/Target/Alpha/Alpha.td
+++ b/lib/Target/Alpha/Alpha.td
@@ -2,8 +2,8 @@
 // 
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
 //
@@ -12,7 +12,7 @@
 
 // Get the target-independent interfaces which we are implementing...
 //
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //Alpha is little endian
 
@@ -20,10 +20,8 @@ include "../Target.td"
 // Subtarget Features
 //===----------------------------------------------------------------------===//
 
-def FeatureCIX : SubtargetFeature<"CIX", "bool", "HasCT",
+def FeatureCIX : SubtargetFeature<"cix", "HasCT", "true",
                                   "Enable CIX extentions">;
-def FeatureFIX : SubtargetFeature<"FIX", "bool", "HasF2I",
-                                  "Enable FIX extentions">;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
@@ -31,6 +29,12 @@ def FeatureFIX : SubtargetFeature<"FIX", "bool", "HasF2I",
 
 include "AlphaRegisterInfo.td"
 
+//===----------------------------------------------------------------------===//
+// Schedule Description
+//===----------------------------------------------------------------------===//
+
+include "AlphaSchedule.td"
+
 //===----------------------------------------------------------------------===//
 // Instruction Descriptions
 //===----------------------------------------------------------------------===//
@@ -47,11 +51,9 @@ def AlphaInstrInfo : InstrInfo {
 // Alpha Processor Definitions
 //===----------------------------------------------------------------------===//
 
-def : Processor<"generic", NoItineraries, []>;
-def : Processor<"pca56"  , NoItineraries, []>;
-def : Processor<"ev56"   , NoItineraries, []>;
-def : Processor<"ev6"    , NoItineraries, [FeatureFIX]>;
-def : Processor<"ev67"   , NoItineraries, [FeatureFIX, FeatureCIX]>;
+def : Processor<"generic", Alpha21264Itineraries, []>;
+def : Processor<"ev6"    , Alpha21264Itineraries, []>;
+def : Processor<"ev67"   , Alpha21264Itineraries, [FeatureCIX]>;
 
 //===----------------------------------------------------------------------===//
 // The Alpha Target
@@ -59,20 +61,6 @@ def : Processor<"ev67"   , NoItineraries, [FeatureFIX, FeatureCIX]>;
 
 
 def Alpha : Target {
-  // Pointers on Alpha are 64-bits in size.
-  let PointerType = i64;
-
-  let CalleeSavedRegisters = 
-       //saved regs
-       [R9, R10, R11, R12, R13, R14, 
-       //Frame pointer
-//     R15, 
-       //return address
-//     R26, 
-       //Stack Pointer
-//     R30,
-         F2, F3, F4, F5, F6, F7, F8, F9];
-
   // Pull in Instruction Info:
   let InstructionSet = AlphaInstrInfo;
 }