Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.

[oota-llvm.git] / lib / Target / Alpha / AlphaCodeEmitter.cpp

diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp
index b51440932f7964f21486ffae7efa970842ae6c35..ea828c804c796b743bac127005debbc785e21ee5 100644 (file)
--- a/lib/Target/Alpha/AlphaCodeEmitter.cpp
+++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp
@@ -18,31 +18,52 @@
 #include "Alpha.h"
 #include "llvm/PassManager.h"
 #include "llvm/CodeGen/MachineCodeEmitter.h"
+#include "llvm/CodeGen/JITCodeEmitter.h"
+#include "llvm/CodeGen/ObjectCodeEmitter.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/Function.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
 namespace {
-  class AlphaCodeEmitter : public MachineFunctionPass {
-    const AlphaInstrInfo  *II;
-    TargetMachine &TM;
-    MachineCodeEmitter  &MCE;
+
+  class AlphaCodeEmitter {
+    MachineCodeEmitter &MCE;
+  public:
+    AlphaCodeEmitter(MachineCodeEmitter &mce) : MCE(mce) {}
+
+    /// getBinaryCodeForInstr - This function, generated by the
+    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
+    /// machine instructions.
+
+    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
 
     /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
-    ///
+
     unsigned getMachineOpValue(const MachineInstr &MI,
                                const MachineOperand &MO);
+  };
+
+  template <class CodeEmitter>
+  class Emitter : public MachineFunctionPass, public AlphaCodeEmitter
+  {
+    const AlphaInstrInfo  *II;
+    TargetMachine         &TM;
+    CodeEmitter           &MCE;
 
   public:
     static char ID;
-    explicit AlphaCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
-      : MachineFunctionPass(&ID), II(0), TM(tm), MCE(mce) {}
-    AlphaCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
-                     const AlphaInstrInfo& ii)
-      : MachineFunctionPass(&ID), II(&ii), TM(tm), MCE(mce) {}
+    explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
+      : MachineFunctionPass(&ID), AlphaCodeEmitter(mce),
+        II(0), TM(tm), MCE(mce) {}
+    Emitter(TargetMachine &tm, CodeEmitter &mce, const AlphaInstrInfo& ii)
+      : MachineFunctionPass(&ID), AlphaCodeEmitter(mce),
+        II(&ii), TM(tm), MCE(mce) {}
 
     bool runOnMachineFunction(MachineFunction &MF);
 
@@ -50,29 +71,33 @@ namespace {
       return "Alpha Machine Code Emitter";
     }
 
-    void emitInstruction(const MachineInstr &MI);
-
-    /// getBinaryCodeForInstr - This function, generated by the
-    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
-    /// machine instructions.
-    ///
-    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
-
   private:
     void emitBasicBlock(MachineBasicBlock &MBB);
-
   };
-  char AlphaCodeEmitter::ID = 0;
+
+  template <class CodeEmitter>
+    char Emitter<CodeEmitter>::ID = 0;
 }
 
-/// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha code
-/// to the specified MCE object.
+/// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha
+/// code to the specified MCE object.
+
 FunctionPass *llvm::createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
                                                MachineCodeEmitter &MCE) {
-  return new AlphaCodeEmitter(TM, MCE);
+  return new Emitter<MachineCodeEmitter>(TM, MCE);
+}
+
+FunctionPass *llvm::createAlphaJITCodeEmitterPass(AlphaTargetMachine &TM,
+                                                  JITCodeEmitter &JCE) {
+  return new Emitter<JITCodeEmitter>(TM, JCE);
+}
+FunctionPass *llvm::createAlphaObjectCodeEmitterPass(AlphaTargetMachine &TM,
+                                                     ObjectCodeEmitter &OCE) {
+  return new Emitter<ObjectCodeEmitter>(TM, OCE);
 }
 
-bool AlphaCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
+template <class CodeEmitter>
+bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
   II = ((AlphaTargetMachine&)MF.getTarget()).getInstrInfo();
 
   do {
@@ -84,11 +109,13 @@ bool AlphaCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
   return false;
 }
 
-void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
+template <class CodeEmitter>
+void Emitter<CodeEmitter>::emitBasicBlock(MachineBasicBlock &MBB) {
   MCE.StartMachineBasicBlock(&MBB);
   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
        I != E; ++I) {
     const MachineInstr &MI = *I;
+    MCE.processDebugLoc(MI.getDebugLoc(), true);
     switch(MI.getOpcode()) {
     default:
       MCE.emitWordLE(getBinaryCodeForInstr(*I));
@@ -97,8 +124,10 @@ void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
     case Alpha::PCLABEL:
     case Alpha::MEMLABEL:
     case TargetInstrInfo::IMPLICIT_DEF:
+    case TargetInstrInfo::KILL:
       break; //skip these
     }
+    MCE.processDebugLoc(MI.getDebugLoc(), false);
   }
 }
 
@@ -137,8 +166,7 @@ static unsigned getAlphaRegNumber(unsigned Reg) {
   case Alpha::R30 : case Alpha::F30 : return 30;
   case Alpha::R31 : case Alpha::F31 : return 31;
   default:
-    assert(0 && "Unhandled reg");
-    abort();
+    llvm_unreachable("Unhandled reg");
   }
 }
 
@@ -148,13 +176,12 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
   unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
                    // or things that get fixed up later by the JIT.
 
-  if (MO.isRegister()) {
+  if (MO.isReg()) {
     rv = getAlphaRegNumber(MO.getReg());
-  } else if (MO.isImmediate()) {
+  } else if (MO.isImm()) {
     rv = MO.getImm();
-  } else if (MO.isGlobalAddress() || MO.isExternalSymbol()
-             || MO.isConstantPoolIndex()) {
-    DOUT << MO << " is a relocated op for " << MI << "\n";
+  } else if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
+    DEBUG(errs() << MO << " is a relocated op for " << MI << "\n");
     unsigned Reloc = 0;
     int Offset = 0;
     bool useGOT = false;
@@ -190,32 +217,31 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
       Offset = MI.getOperand(3).getImm();
       break;
     default:
-      assert(0 && "unknown relocatable instruction");
-      abort();
+      llvm_unreachable("unknown relocatable instruction");
     }
-    if (MO.isGlobalAddress())
+    if (MO.isGlobal())
       MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
                                                  Reloc, MO.getGlobal(), Offset,
                                                  isa<Function>(MO.getGlobal()),
                                                  useGOT));
-    else if (MO.isExternalSymbol())
+    else if (MO.isSymbol())
       MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
                                                      Reloc, MO.getSymbolName(),
                                                      Offset, true));
     else
      MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
                                           Reloc, MO.getIndex(), Offset));
-  } else if (MO.isMachineBasicBlock()) {
+  } else if (MO.isMBB()) {
     MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
                                                Alpha::reloc_bsr, MO.getMBB()));
-  }else {
-    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
-    abort();
+  } else {
+#ifndef NDEBUG
+    errs() << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
+#endif
+    llvm_unreachable(0);
   }
 
   return rv;
 }
 
-
 #include "AlphaGenCodeEmitter.inc"
-