Fix spelling and grammar in a comment.

[oota-llvm.git] / lib / Target / Alpha / AlphaISelDAGToDAG.cpp

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index df976fd31e8f65a07dea3f0d7a6e2d66698baf3c..c7eefccd4095119606733f1a4c69b6d1272bd839 100644 (file)
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by Andrew Lenharth and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -18,7 +18,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Target/TargetOptions.h"
@@ -26,6 +26,7 @@
 #include "llvm/DerivedTypes.h"
 #include "llvm/GlobalValue.h"
 #include "llvm/Intrinsics.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MathExtras.h"
 #include <algorithm>
@@ -90,7 +91,9 @@ namespace {
       // see if the missing bits (0x1000) are already known zero if not, the zap
       // isn't okay to do, as it won't clear all the required bits.
       if (BitsToCheck &&
-          !CurDAG->MaskedValueIsZero(LHS, BitsToCheck))
+          !CurDAG->MaskedValueIsZero(LHS,
+                                     APInt(LHS.getValueSizeInBits(),
+                                           BitsToCheck)))
         return 0;
       
       return Result;
@@ -143,9 +146,9 @@ namespace {
     }
 
   public:
-    AlphaDAGToDAGISel(TargetMachine &TM)
+    explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
       : SelectionDAGISel(AlphaLowering), 
-        AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering())) 
+        AlphaLowering(*TM.getTargetLowering())
     {}
 
     /// getI64Imm - Return a target constant with the specified value, of type
@@ -200,10 +203,9 @@ private:
 /// GOT address into a register.
 ///
 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
-  MachineFunction* MF = BB->getParent();
   unsigned GP = 0;
-  for(MachineFunction::livein_iterator ii = MF->livein_begin(), 
-        ee = MF->livein_end(); ii != ee; ++ii)
+  for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), 
+        ee = RegInfo->livein_end(); ii != ee; ++ii)
     if (ii->first == Alpha::R29) {
       GP = ii->second;
       break;
@@ -216,10 +218,9 @@ SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
 /// getRASaveReg - Grab the return address
 ///
 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
-  MachineFunction* MF = BB->getParent();
   unsigned RA = 0;
-  for(MachineFunction::livein_iterator ii = MF->livein_begin(), 
-        ee = MF->livein_end(); ii != ee; ++ii)
+  for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), 
+        ee = RegInfo->livein_end(); ii != ee; ++ii)
     if (ii->first == Alpha::R26) {
       RA = ii->second;
       break;
@@ -333,7 +334,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
   case ISD::TargetConstantFP: {
     ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
     bool isDouble = N->getValueType(0) == MVT::f64;
-    MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
+    MVT T = isDouble ? MVT::f64 : MVT::f32;
     if (CN->getValueAPF().isPosZero()) {
       return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
                                   T, CurDAG->getRegister(Alpha::F31, T),
@@ -349,7 +350,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
   }
 
   case ISD::SETCC:
-    if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
+    if (N->getOperand(0).Val->getValueType(0).isFloatingPoint()) {
       ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
 
       unsigned Opc = Alpha::WTF;
@@ -403,9 +404,9 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
     break;
 
   case ISD::SELECT:
-    if (MVT::isFloatingPoint(N->getValueType(0)) &&
+    if (N->getValueType(0).isFloatingPoint() &&
         (N->getOperand(0).getOpcode() != ISD::SETCC ||
-         !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
+         !N->getOperand(0).getOperand(1).getValueType().isFloatingPoint())) {
       //This should be the condition not covered by the Patterns
       //FIXME: Don't have SelectCode die, but rather return something testable
       // so that things like this can be caught in fall though code
@@ -471,7 +472,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
   AddToISelQueue(Chain);
 
    std::vector<SDOperand> CallOperands;
-   std::vector<MVT::ValueType> TypeOperands;
+   std::vector<MVT> TypeOperands;
   
    //grab the arguments
    for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
@@ -488,7 +489,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
    
    for (int i = 6; i < count; ++i) {
      unsigned Opc = Alpha::WTF;
-     if (MVT::isInteger(TypeOperands[i])) {
+     if (TypeOperands[i].isInteger()) {
        Opc = Alpha::STQ;
      } else if (TypeOperands[i] == MVT::f32) {
        Opc = Alpha::STS;
@@ -503,7 +504,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
      Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
    }
    for (int i = 0; i < std::min(6, count); ++i) {
-     if (MVT::isInteger(TypeOperands[i])) {
+     if (TypeOperands[i].isInteger()) {
        Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
        InFlag = Chain.getValue(1);
      } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
@@ -532,7 +533,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
 
    std::vector<SDOperand> CallResults;
   
-   switch (N->getValueType(0)) {
+   switch (N->getValueType(0).getSimpleVT()) {
    default: assert(0 && "Unexpected ret value!");
      case MVT::Other: break;
    case MVT::i64:
@@ -558,6 +559,6 @@ void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
 /// createAlphaISelDag - This pass converts a legalized DAG into a 
 /// Alpha-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
+FunctionPass *llvm::createAlphaISelDag(AlphaTargetMachine &TM) {
   return new AlphaDAGToDAGISel(TM);
 }