#include "AlphaTargetMachine.h"
#include "AlphaISelLowering.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/SelectionDAG.h"
//===--------------------------------------------------------------------===//
/// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
/// instructions for SelectionDAG operations.
- ///
class AlphaDAGToDAGISel : public SelectionDAGISel {
AlphaTargetLowering AlphaLowering;
+ static const int64_t IMM_LOW = -32768;
+ static const int64_t IMM_HIGH = 32767;
+ static const int64_t IMM_MULT = 65536;
+
public:
AlphaDAGToDAGISel(TargetMachine &TM)
- : SelectionDAGISel(AlphaLowering), AlphaLowering(TM) {}
+ : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
+ {}
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
private:
SDOperand getGlobalBaseReg();
+ SDOperand getRASaveReg();
SDOperand SelectCALL(SDOperand Op);
};
/// GOT address into a register.
///
SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
- return CurDAG->getRegister(AlphaLowering.getVRegGP(), MVT::i64);
+ return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ AlphaLowering.getVRegGP(),
+ MVT::i64);
+}
+
+/// getRASaveReg - Grab the return address
+///
+SDOperand AlphaDAGToDAGISel::getRASaveReg() {
+ return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ AlphaLowering.getVRegRA(),
+ MVT::i64);
}
/// InstructionSelectBasicBlock - This callback is invoked by
case ISD::TAILCALL:
case ISD::CALL: return SelectCALL(Op);
- case ISD::DYNAMIC_STACKALLOC:
- assert(0 && "You want these too?");
-
- case ISD::SETCC: {
- ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
- assert(MVT::isInteger(N->getOperand(0).getValueType()) && "FP numbers are unnecessary");
- SDOperand Op1 = Select(N->getOperand(0));
- SDOperand Op2 = Select(N->getOperand(1));
- unsigned Opc = Alpha::WTF;
- int dir;
- switch (CC) {
- default: N->dump(); assert(0 && "Unknown integer comparison!");
- case ISD::SETEQ: Opc = Alpha::CMPEQ; dir=1; break;
- case ISD::SETLT: Opc = Alpha::CMPLT; dir = 1; break;
- case ISD::SETLE: Opc = Alpha::CMPLE; dir = 1; break;
- case ISD::SETGT: Opc = Alpha::CMPLT; dir = 0; break;
- case ISD::SETGE: Opc = Alpha::CMPLE; dir = 0; break;
- case ISD::SETULT: Opc = Alpha::CMPULT; dir = 1; break;
- case ISD::SETUGT: Opc = Alpha::CMPULT; dir = 0; break;
- case ISD::SETULE: Opc = Alpha::CMPULE; dir = 1; break;
- case ISD::SETUGE: Opc = Alpha::CMPULE; dir = 0; break;
- case ISD::SETNE: {//Handle this one special
- SDOperand Tmp = CurDAG->getTargetNode(Alpha::CMPEQ, MVT::i64, Op1, Op2);
- CurDAG->SelectNodeTo(N, Alpha::CMPEQ, MVT::i64, CurDAG->getRegister(Alpha::R31, MVT::i64), Tmp);
- return SDOperand(N, 0);
+ case ISD::DYNAMIC_STACKALLOC: {
+ if (!isa<ConstantSDNode>(N->getOperand(2)) ||
+ cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
+ std::cerr << "Cannot allocate stack object with greater alignment than"
+ << " the stack alignment yet!";
+ abort();
}
- }
- CurDAG->SelectNodeTo(N, Opc, MVT::i64, dir ? Op1 : Op2, dir ? Op2 : Op1);
- return SDOperand(N, 0);
- }
- case ISD::BRCOND: {
SDOperand Chain = Select(N->getOperand(0));
- SDOperand CC = Select(N->getOperand(1));
- CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC, Chain);
- return SDOperand(N, 0);
- }
- case ISD::LOAD:
- case ISD::EXTLOAD:
- case ISD::ZEXTLOAD:
- case ISD::SEXTLOAD: {
- SDOperand Chain = Select(N->getOperand(0));
- SDOperand Address = Select(N->getOperand(1));
- unsigned opcode = N->getOpcode();
- unsigned Opc = Alpha::WTF;
- if (opcode == ISD::LOAD)
- switch (N->getValueType(0)) {
- default: N->dump(); assert(0 && "Bad load!");
- case MVT::i64: Opc = Alpha::LDQ; break;
- case MVT::f64: Opc = Alpha::LDT; break;
- case MVT::f32: Opc = Alpha::LDS; break;
- }
- else
- switch (cast<VTSDNode>(N->getOperand(3))->getVT()) {
- default: N->dump(); assert(0 && "Bad sign extend!");
- case MVT::i32: Opc = Alpha::LDL;
- assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
- case MVT::i16: Opc = Alpha::LDWU;
- assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
- case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
- case MVT::i8: Opc = Alpha::LDBU;
- assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
- }
-
- CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
- getI64Imm(0), Address, Chain);
- return SDOperand(N, Op.ResNo);
+ SDOperand Amt = Select(N->getOperand(1));
+ SDOperand Reg = CurDAG->getRegister(Alpha::R30, MVT::i64);
+ SDOperand Val = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
+ Chain = Val.getValue(1);
+
+ // Subtract the amount (guaranteed to be a multiple of the stack alignment)
+ // from the stack pointer, giving us the result pointer.
+ SDOperand Result = CurDAG->getTargetNode(Alpha::SUBQ, MVT::i64, Val, Amt);
+
+ // Copy this result back into R30.
+ Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result);
+
+ // Copy this result back out of R30 to make sure we're not using the stack
+ // space without decrementing the stack pointer.
+ Result = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
+
+ // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
+ CodeGenMap[Op.getValue(0)] = Result;
+ CodeGenMap[Op.getValue(1)] = Result.getValue(1);
+ return SDOperand(Result.Val, Op.ResNo);
}
+ case ISD::BRCOND: {
+ if (N->getOperand(1).getOpcode() == ISD::SETCC &&
+ MVT::isFloatingPoint(N->getOperand(1).getOperand(0).getValueType())) {
+ SDOperand Chain = Select(N->getOperand(0));
+ SDOperand CC1 = Select(N->getOperand(1).getOperand(0));
+ SDOperand CC2 = Select(N->getOperand(1).getOperand(1));
+ ISD::CondCode cCode= cast<CondCodeSDNode>(N->getOperand(1).getOperand(2))->get();
- case ISD::BR: {
- CurDAG->SelectNodeTo(N, Alpha::BR_DAG, MVT::Other, N->getOperand(1),
- Select(N->getOperand(0)));
- return SDOperand(N, 0);
- }
+ bool rev = false;
+ bool isNE = false;
+ unsigned Opc = Alpha::WTF;
+ switch(cCode) {
+ default: N->dump(); assert(0 && "Unknown FP comparison!");
+ case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
+ case ISD::SETLT: Opc = Alpha::CMPTLT; break;
+ case ISD::SETLE: Opc = Alpha::CMPTLE; break;
+ case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
+ case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
+ case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
+ };
+ SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64,
+ rev?CC2:CC1,
+ rev?CC1:CC2);
- case ISD::TokenFactor: {
- SDOperand New;
- if (N->getNumOperands() == 2) {
- SDOperand Op0 = Select(N->getOperand(0));
- SDOperand Op1 = Select(N->getOperand(1));
- New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
- } else {
- std::vector<SDOperand> Ops;
- for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
- Ops.push_back(Select(N->getOperand(i)));
- New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
+ MachineBasicBlock *Dest =
+ cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
+ if(isNE)
+ return CurDAG->SelectNodeTo(N, Alpha::FBEQ, MVT::Other, cmp,
+ CurDAG->getBasicBlock(Dest), Chain);
+ else
+ return CurDAG->SelectNodeTo(N, Alpha::FBNE, MVT::Other, cmp,
+ CurDAG->getBasicBlock(Dest), Chain);
}
-
- CodeGenMap[Op] = New;
- return New;
- }
- case ISD::CopyFromReg: {
- SDOperand Chain = Select(N->getOperand(0));
- if (Chain == N->getOperand(0)) return Op; // No change
- SDOperand New = CurDAG->getCopyFromReg(Chain,
- cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
- return New.getValue(Op.ResNo);
- }
- case ISD::CopyToReg: {
SDOperand Chain = Select(N->getOperand(0));
- SDOperand Reg = N->getOperand(1);
- SDOperand Val = Select(N->getOperand(2));
- SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
- Chain, Reg, Val);
- CodeGenMap[Op] = New;
- return New;
+ SDOperand CC = Select(N->getOperand(1));
+ MachineBasicBlock *Dest =
+ cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
+ return CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC,
+ CurDAG->getBasicBlock(Dest), Chain);
}
- case ISD::UNDEF:
- if (N->getValueType(0) == MVT::i64)
- CurDAG->SelectNodeTo(N, Alpha::IDEF, MVT::i64);
-// else if (N->getValueType(0) == MVT::f32)
-// CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F4, MVT::f32);
-// else
-// CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F8, MVT::f64);
- return SDOperand(N, 0);
+
case ISD::FrameIndex: {
-// int FI = cast<FrameIndexSDNode>(N)->getIndex();
-// CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
-// CurDAG->getTargetFrameIndex(FI, MVT::i32),
-// getI32Imm(0));
-// return SDOperand(N, 0);
- assert(0 && "Frame?, you are suppose to look through the window, not at the frame!");
+ int FI = cast<FrameIndexSDNode>(N)->getIndex();
+ return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
+ CurDAG->getTargetFrameIndex(FI, MVT::i32),
+ getI64Imm(0));
}
- case ISD::ConstantPool: {
-// Constant *C = cast<ConstantPoolSDNode>(N)->get();
-// SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32);
-// if (PICEnabled)
-// Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
-// else
-// Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
-// CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
-// return SDOperand(N, 0);
- assert(0 && "Constants are overrated");
- }
- case ISD::GlobalAddress: {
- GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
- SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
- CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, GA, getGlobalBaseReg());
- return SDOperand(N, 0);
- }
- case ISD::ExternalSymbol:
- CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64,
- CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(), MVT::i64),
- CurDAG->getRegister(AlphaLowering.getVRegGP(), MVT::i64));
- return SDOperand(N, 0);
-
- case ISD::CALLSEQ_START:
- case ISD::CALLSEQ_END: {
- unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
- unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
- Alpha::ADJUSTSTACKDOWN : Alpha::ADJUSTSTACKUP;
- CurDAG->SelectNodeTo(N, Opc, MVT::Other,
- getI64Imm(Amt), Select(N->getOperand(0)));
- return SDOperand(N, 0);
+ case AlphaISD::GlobalBaseReg:
+ return getGlobalBaseReg();
+
+ case AlphaISD::DivCall: {
+ SDOperand Chain = CurDAG->getEntryNode();
+ Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, Select(Op.getOperand(1)),
+ SDOperand(0,0));
+ Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, Select(Op.getOperand(2)),
+ Chain.getValue(1));
+ Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Select(Op.getOperand(0)),
+ Chain.getValue(1));
+ Chain = CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
+ Chain, Chain.getValue(1));
+ Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
+ Chain.getValue(1));
+ return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
}
+
case ISD::RET: {
SDOperand Chain = Select(N->getOperand(0)); // Token chain.
+ SDOperand InFlag;
if (N->getNumOperands() == 2) {
SDOperand Val = Select(N->getOperand(1));
if (N->getOperand(1).getValueType() == MVT::i64) {
- Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val);
+ Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
+ InFlag = Chain.getValue(1);
+ } else if (N->getOperand(1).getValueType() == MVT::f64 ||
+ N->getOperand(1).getValueType() == MVT::f32) {
+ Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag);
+ InFlag = Chain.getValue(1);
}
}
- //BuildMI(BB, Alpha::RET, 2, Alpha::R31).addReg(Alpha::R26).addImm(1);
-
- // FIXME: add restoring of the RA to R26 to the chain
+ Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
+ InFlag = Chain.getValue(1);
+
// Finally, select this to a ret instruction.
- CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain);
- return SDOperand(N, 0);
+ return CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
+ }
+ case ISD::Constant: {
+ uint64_t uval = cast<ConstantSDNode>(N)->getValue();
+ int64_t val = (int64_t)uval;
+ int32_t val32 = (int32_t)val;
+ if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
+ val >= IMM_LOW + IMM_LOW * IMM_MULT)
+ break; //(LDAH (LDA))
+ if ((uval >> 32) == 0 && //empty upper bits
+ val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
+ val32 >= IMM_LOW + IMM_LOW * IMM_MULT)
+ break; //(zext (LDAH (LDA)))
+ //Else use the constant pool
+ MachineConstantPool *CP = BB->getParent()->getConstantPool();
+ ConstantUInt *C =
+ ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
+ SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
+ Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
+ return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
+ CPI, Tmp, CurDAG->getEntryNode());
}
+ case ISD::ConstantFP:
+ if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
+ bool isDouble = N->getValueType(0) == MVT::f64;
+ MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
+ if (CN->isExactlyValue(+0.0)) {
+ return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
+ T, CurDAG->getRegister(Alpha::F31, T),
+ CurDAG->getRegister(Alpha::F31, T));
+ } else if ( CN->isExactlyValue(-0.0)) {
+ return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
+ T, CurDAG->getRegister(Alpha::F31, T),
+ CurDAG->getRegister(Alpha::F31, T));
+ } else {
+ abort();
+ }
+ break;
+ }
+ case ISD::SETCC:
+ if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
+ unsigned Opc = Alpha::WTF;
+ ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
+ bool rev = false;
+ bool isNE = false;
+ switch(CC) {
+ default: N->dump(); assert(0 && "Unknown FP comparison!");
+ case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
+ case ISD::SETLT: Opc = Alpha::CMPTLT; break;
+ case ISD::SETLE: Opc = Alpha::CMPTLE; break;
+ case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
+ case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
+ case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
+ };
+ SDOperand tmp1 = Select(N->getOperand(0)),
+ tmp2 = Select(N->getOperand(1));
+ SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64,
+ rev?tmp2:tmp1,
+ rev?tmp1:tmp2);
+ if (isNE)
+ cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, cmp,
+ CurDAG->getRegister(Alpha::F31, MVT::f64));
+
+ SDOperand LD;
+ if (AlphaLowering.hasITOF()) {
+ LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp);
+ } else {
+ int FrameIdx =
+ CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
+ SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
+ SDOperand ST = CurDAG->getTargetNode(Alpha::STT, MVT::Other,
+ cmp, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
+ LD = CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
+ CurDAG->getRegister(Alpha::R31, MVT::i64),
+ ST);
+ }
+ SDOperand FP = CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
+ CurDAG->getRegister(Alpha::R31, MVT::i64),
+ LD);
+ return FP;
+ }
+ break;
+ case ISD::SELECT:
+ if (MVT::isFloatingPoint(N->getValueType(0)) &&
+ (N->getOperand(0).getOpcode() != ISD::SETCC ||
+ !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
+ //This should be the condition not covered by the Patterns
+ //FIXME: Don't have SelectCode die, but rather return something testable
+ // so that things like this can be caught in fall though code
+ //move int to fp
+ bool isDouble = N->getValueType(0) == MVT::f64;
+ SDOperand LD,
+ cond = Select(N->getOperand(0)),
+ TV = Select(N->getOperand(1)),
+ FV = Select(N->getOperand(2));
+
+ if (AlphaLowering.hasITOF()) {
+ LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
+ } else {
+ int FrameIdx =
+ CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
+ SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
+ SDOperand ST = CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
+ cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
+ LD = CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
+ CurDAG->getRegister(Alpha::R31, MVT::i64),
+ ST);
+ }
+ SDOperand FP = CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
+ MVT::f64, FV, TV, LD);
+ return FP;
+ }
+ break;
}
-
+
return SelectCode(Op);
}
SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
+ //TODO: add flag stuff to prevent nondeturministic breakage!
+
SDNode *N = Op.Val;
SDOperand Chain = Select(N->getOperand(0));
- SDOperand Addr = Select(N->getOperand(1));
+ SDOperand Addr = N->getOperand(1);
+ SDOperand InFlag; // Null incoming flag value.
-// unsigned CallOpcode;
std::vector<SDOperand> CallOperands;
std::vector<MVT::ValueType> TypeOperands;
static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
Alpha::F19, Alpha::F20, Alpha::F21};
+ for (int i = 6; i < count; ++i) {
+ unsigned Opc = Alpha::WTF;
+ if (MVT::isInteger(TypeOperands[i])) {
+ Opc = Alpha::STQ;
+ } else if (TypeOperands[i] == MVT::f32) {
+ Opc = Alpha::STS;
+ } else if (TypeOperands[i] == MVT::f64) {
+ Opc = Alpha::STT;
+ } else
+ assert(0 && "Unknown operand");
+ Chain = CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
+ getI64Imm((i - 6) * 8),
+ CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
+ Chain);
+ }
for (int i = 0; i < std::min(6, count); ++i) {
if (MVT::isInteger(TypeOperands[i])) {
- Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i]);
- } else {
- assert(0 && "No FP support yet");
- }
+ Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
+ InFlag = Chain.getValue(1);
+ } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
+ Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
+ InFlag = Chain.getValue(1);
+ } else
+ assert(0 && "Unknown operand");
}
- assert(CallOperands.size() <= 6 && "Too big a call");
- Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr);
+
// Finally, once everything is in registers to pass to the call, emit the
// call itself.
- Chain = CurDAG->getTargetNode(Alpha::JSRDAG, MVT::Other, Chain );
-
+ if (Addr.getOpcode() == AlphaISD::GPRelLo) {
+ SDOperand GOT = getGlobalBaseReg();
+ Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
+ InFlag = Chain.getValue(1);
+ Chain = CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
+ Addr.getOperand(0), Chain, InFlag);
+ } else {
+ Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Select(Addr), InFlag);
+ InFlag = Chain.getValue(1);
+ Chain = CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
+ Chain, InFlag );
+ }
+ InFlag = Chain.getValue(1);
+
std::vector<SDOperand> CallResults;
switch (N->getValueType(0)) {
default: assert(0 && "Unexpected ret value!");
case MVT::Other: break;
case MVT::i64:
- Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64).getValue(1);
+ Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
+ CallResults.push_back(Chain.getValue(0));
+ break;
+ case MVT::f32:
+ Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
+ CallResults.push_back(Chain.getValue(0));
+ break;
+ case MVT::f64:
+ Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
CallResults.push_back(Chain.getValue(0));
break;
}
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