Misc. SSE2 intrinsics: clflush, lfench, mfence

[oota-llvm.git] / lib / Target / Alpha / AlphaInstrFormats.td

diff --git a/lib/Target/Alpha/AlphaInstrFormats.td b/lib/Target/Alpha/AlphaInstrFormats.td
index abf24095ebde62daed13200dece751a4ff53a0cc..663562948d47adf5ec7b5cee580ae976f6c99471 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrFormats.td
+++ b/lib/Target/Alpha/AlphaInstrFormats.td
@@ -17,29 +17,33 @@
 //Floating-point
 //PALcode
 
-def u8imm   : Operand<i8>;
-def s14imm  : Operand<i16>;
-def s16imm  : Operand<i16>;
-def s21imm  : Operand<i32>;
+def u8imm   : Operand<i64>;
+def s14imm  : Operand<i64>;
+def s16imm  : Operand<i64>;
+def s21imm  : Operand<i64>;
 def s64imm  : Operand<i64>;
 
 //===----------------------------------------------------------------------===//
 // Instruction format superclass
 //===----------------------------------------------------------------------===//
-
-class InstAlpha<bits<6> op, dag OL, string asmstr> : Instruction {          // Alpha instruction baseline
+// Alpha instruction baseline
+class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction {
   field bits<32> Inst;
   let Namespace = "Alpha";
-  let OperandList = OL;
   let AsmString = asmstr;
-
- 
   let Inst{31-26} = op;
+  let Itinerary = itin;
 }
 
+
 //3.3.1
-class MForm<bits<6> opcode, string asmstr> 
-        : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), asmstr> {
+class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag> pattern, InstrItinClass itin> 
+        : InstAlpha<opcode, asmstr, itin> {
+  let Pattern = pattern;
+  let isStore = store;
+  let isLoad = load;
+  let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
+
   bits<5> Ra;
   bits<16> disp;
   bits<5> Rb;
@@ -48,23 +52,24 @@ class MForm<bits<6> opcode, string asmstr>
   let Inst{20-16} = Rb;
   let Inst{15-0} = disp;
 }
-
-class MgForm<bits<6> opcode, string asmstr> 
-        : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM), asmstr> {
+class MfcForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin> 
+        : InstAlpha<opcode, asmstr, itin> {    
   bits<5> Ra;
-  bits<16> disp;
-  bits<5> Rb;
 
+  let OperandList = (ops GPRC:$RA);
   let Inst{25-21} = Ra;
-  let Inst{20-16} = Rb;
-  let Inst{15-0} = disp;
+  let Inst{20-16} = 0;
+  let Inst{15-0} = fc;
 }
 
-class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
+class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass itin>
+    : InstAlpha<opcode, asmstr, itin> {
   bits<5> Ra;
   bits<5> Rb;
   bits<14> disp;
 
+  let OperandList = OL;
+
   let Inst{25-21} = Ra;
   let Inst{20-16} = Rb;
   let Inst{15-14} = TB;
@@ -72,9 +77,24 @@ class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr> : InstAlpha<opc
 }
 
 //3.3.2
+def target : Operand<OtherVT> {}
 let isBranch = 1, isTerminator = 1 in
-class BForm<bits<6> opcode, string asmstr> 
-    : InstAlpha<opcode, (ops GPRC:$RA, s21imm:$DISP), asmstr> {
+class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
+  let Pattern = pattern;
+  let OperandList = (ops target:$DISP);
+  bits<5> Ra;
+  bits<21> disp;
+
+  let Inst{25-21} = Ra;
+  let Inst{20-0} = disp;
+}
+let isBranch = 1, isTerminator = 1 in
+class BForm<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
+  let Pattern = pattern;
+  let OperandList = (ops GPRC:$RA, target:$DISP);
+
   bits<5> Ra;
   bits<21> disp;
 
@@ -83,8 +103,11 @@ class BForm<bits<6> opcode, string asmstr>
 }
 
 let isBranch = 1, isTerminator = 1 in
-class FBForm<bits<6> opcode, string asmstr> 
-    : InstAlpha<opcode, (ops FPRC:$RA, s21imm:$DISP), asmstr> {
+class FBForm<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
+  let Pattern = pattern;
+  let OperandList = (ops F8RC:$RA, target:$DISP);
+
   bits<5> Ra;
   bits<21> disp;
 
@@ -93,8 +116,11 @@ class FBForm<bits<6> opcode, string asmstr>
 }
 
 //3.3.3
-class OForm<bits<6> opcode, bits<7> fun, string asmstr> 
-        : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), asmstr> {
+class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
+  let Pattern = pattern;
+  let OperandList = (ops GPRC:$RC, GPRC:$RA, GPRC:$RB);
+
   bits<5> Rc;
   bits<5> Ra;
   bits<5> Rb;
@@ -108,13 +134,34 @@ class OForm<bits<6> opcode, bits<7> fun, string asmstr>
   let Inst{4-0} = Rc;
 }
 
-class OcmForm<bits<6> opcode, bits<7> fun, dag OL, string asmstr> 
-        : InstAlpha<opcode, OL, asmstr> {
-  bits<5> Ra;
+class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
+  let Pattern = pattern;
+  let OperandList = (ops GPRC:$RC, GPRC:$RB);
+
+  bits<5> Rc;
   bits<5> Rb;
   bits<7> Function = fun;
+
+  let Inst{25-21} = 31;
+  let Inst{20-16} = Rb;
+  let Inst{15-13} = 0;
+  let Inst{12} = 0;
+  let Inst{11-5} = Function;
+  let Inst{4-0} = Rc;
+}
+
+class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
+  let Pattern = pattern;
+  let OperandList = (ops GPRC:$RDEST, GPRC:$RFALSE, GPRC:$RTRUE, GPRC:$RCOND);
+
   bits<5> Rc;
+  bits<5> Rb;
+  bits<5> Ra;
+  bits<7> Function = fun;
 
+  let isTwoAddress = 1;
   let Inst{25-21} = Ra;
   let Inst{20-16} = Rb;
   let Inst{15-13} = 0;
@@ -124,8 +171,11 @@ class OcmForm<bits<6> opcode, bits<7> fun, dag OL, string asmstr>
 }
 
 
-class OFormL<bits<6> opcode, bits<7> fun, string asmstr> 
-        : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), asmstr> {
+class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
+  let Pattern = pattern;
+  let OperandList = (ops GPRC:$RC, GPRC:$RA, u8imm:$L);
+
   bits<5> Rc;
   bits<5> Ra;
   bits<8> LIT;
@@ -138,13 +188,17 @@ class OFormL<bits<6> opcode, bits<7> fun, string asmstr>
   let Inst{4-0} = Rc;
 }
 
-class OcmFormL<bits<6> opcode, bits<7> fun, dag OL, string asmstr> 
-        : InstAlpha<opcode, OL, asmstr> {
-  bits<5> Ra;
+class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
+  let Pattern = pattern;
+  let OperandList = (ops GPRC:$RDEST, GPRC:$RFALSE, s64imm:$RTRUE, GPRC:$RCOND);
+ 
+  bits<5> Rc;
   bits<8> LIT;
+  bits<5> Ra;
   bits<7> Function = fun;
-  bits<5> Rc;
 
+  let isTwoAddress = 1;
   let Inst{25-21} = Ra;
   let Inst{20-13} = LIT;
   let Inst{12} = 1;
@@ -153,11 +207,14 @@ class OcmFormL<bits<6> opcode, bits<7> fun, dag OL, string asmstr>
 }
 
 //3.3.4
-class FPForm<bits<6> opcode, bits<11> fun, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
+class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<opcode, asmstr, itin> {
+  let Pattern = pattern;
+
+  bits<5> Fc;
   bits<5> Fa;
   bits<5> Fb;
   bits<11> Function = fun;
-  bits<5> Fc;
 
   let Inst{25-21} = Fa;
   let Inst{20-16} = Fb;
@@ -166,7 +223,9 @@ class FPForm<bits<6> opcode, bits<11> fun, dag OL, string asmstr> : InstAlpha<op
 }
 
 //3.3.5
-class PALForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
+class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+    : InstAlpha<opcode, asmstr, itin> {
+  let OperandList = OL;
   bits<26> Function;
 
   let Inst{25-0} = Function;
@@ -174,5 +233,9 @@ class PALForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asm
 
 
 // Pseudo instructions.
-class PseudoInstAlpha<dag OL, string nm> : InstAlpha<0, OL, nm>  {
+class PseudoInstAlpha<dag OL, string nm, list<dag> pattern, InstrItinClass itin> 
+    : InstAlpha<0, nm, itin>  {
+  let OperandList = OL;
+  let Pattern = pattern;
+
 }