//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
def s16imm : Operand<i64>;
def s21imm : Operand<i64>;
def s64imm : Operand<i64>;
+def u64imm : Operand<i64>;
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
-
-class InstAlpha<bits<6> op, dag OL, string asmstr> : Instruction { // Alpha instruction baseline
+// Alpha instruction baseline
+class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction {
field bits<32> Inst;
let Namespace = "Alpha";
- let OperandList = OL;
let AsmString = asmstr;
-
-
let Inst{31-26} = op;
+ let Itinerary = itin;
}
+
//3.3.1
-class MForm<bits<6> opcode, string asmstr>
- : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), asmstr> {
+class MForm<bits<6> opcode, bit load, string asmstr, list<dag> pattern, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
+ let Pattern = pattern;
+ let canFoldAsLoad = load;
+ let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
+
bits<5> Ra;
bits<16> disp;
bits<5> Rb;
let Inst{20-16} = Rb;
let Inst{15-0} = disp;
}
+class MfcForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
+ bits<5> Ra;
+
+ let OutOperandList = (ops GPRC:$RA);
+ let InOperandList = (ops);
+ let Inst{25-21} = Ra;
+ let Inst{20-16} = 0;
+ let Inst{15-0} = fc;
+}
+class MfcPForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
+ let OutOperandList = (ops);
+ let InOperandList = (ops);
+ let Inst{25-21} = 0;
+ let Inst{20-16} = 0;
+ let Inst{15-0} = fc;
+}
-class MgForm<bits<6> opcode, string asmstr>
- : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM), asmstr> {
+class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
bits<5> Ra;
- bits<16> disp;
bits<5> Rb;
+ bits<14> disp;
+
+ let OutOperandList = (ops);
+ let InOperandList = OL;
let Inst{25-21} = Ra;
let Inst{20-16} = Rb;
- let Inst{15-0} = disp;
+ let Inst{15-14} = TB;
+ let Inst{13-0} = disp;
}
-
-class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
+class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> pattern, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
+ let Pattern=pattern;
bits<5> Ra;
bits<5> Rb;
bits<14> disp;
+ let OutOperandList = (ops);
+ let InOperandList = OL;
+
let Inst{25-21} = Ra;
let Inst{20-16} = Rb;
let Inst{15-14} = TB;
}
//3.3.2
-let isBranch = 1, isTerminator = 1 in
-class BForm<bits<6> opcode, string asmstr>
- : InstAlpha<opcode, (ops GPRC:$RA, s21imm:$DISP), asmstr> {
+def target : Operand<OtherVT> {}
+
+let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
+class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
+ let OutOperandList = (ops);
+ let InOperandList = OL;
+ bits<64> Opc; //dummy
bits<5> Ra;
bits<21> disp;
let Inst{25-21} = Ra;
let Inst{20-0} = disp;
}
-class BFormD<bits<6> opcode, string asmstr>
- : InstAlpha<opcode, (ops s21imm:$DISP), asmstr> {
- bits<5> Ra = 31;
- bits<21> disp;
-
- let Inst{25-21} = Ra;
- let Inst{20-0} = disp;
}
let isBranch = 1, isTerminator = 1 in
-class FBForm<bits<6> opcode, string asmstr>
- : InstAlpha<opcode, (ops FPRC:$RA, s21imm:$DISP), asmstr> {
+class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
+ let Pattern = pattern;
+ let OutOperandList = (ops);
+ let InOperandList = (ops target:$DISP);
bits<5> Ra;
bits<21> disp;
}
//3.3.3
-class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
- : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), asmstr> {
+class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
let Pattern = pattern;
+ let OutOperandList = (outs GPRC:$RC);
+ let InOperandList = (ins GPRC:$RA, GPRC:$RB);
bits<5> Rc;
bits<5> Ra;
let Inst{4-0} = Rc;
}
-class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
- : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RB), asmstr> {
+class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
let Pattern = pattern;
+ let OutOperandList = (outs GPRC:$RC);
+ let InOperandList = (ins GPRC:$RB);
bits<5> Rc;
bits<5> Rb;
let Inst{4-0} = Rc;
}
-class OForm4<bits<6> opcode, bits<7> fun, string asmstr>
- : InstAlpha<opcode, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), asmstr> {
+class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
+ let Pattern = pattern;
+ let OutOperandList = (outs GPRC:$RDEST);
+ let InOperandList = (ins GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE);
+ let Constraints = "$RFALSE = $RDEST";
+ let DisableEncoding = "$RFALSE";
+
bits<5> Rc;
- bits<5> Rb;
bits<5> Ra;
+ bits<5> Rb;
bits<7> Function = fun;
- let isTwoAddress = 1;
+// let isTwoAddress = 1;
let Inst{25-21} = Ra;
let Inst{20-16} = Rb;
let Inst{15-13} = 0;
}
-class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
- : InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), asmstr> {
+class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
let Pattern = pattern;
+ let OutOperandList = (outs GPRC:$RC);
+ let InOperandList = (ins GPRC:$RA, u8imm:$L);
bits<5> Rc;
bits<5> Ra;
let Inst{4-0} = Rc;
}
-class OForm4L<bits<6> opcode, bits<7> fun, string asmstr>
- : InstAlpha<opcode, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), asmstr> {
+class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
+ let Pattern = pattern;
+ let OutOperandList = (outs GPRC:$RDEST);
+ let InOperandList = (ins GPRC:$RCOND, s64imm:$RTRUE, GPRC:$RFALSE);
+ let Constraints = "$RFALSE = $RDEST";
+ let DisableEncoding = "$RFALSE";
+
bits<5> Rc;
- bits<8> LIT;
bits<5> Ra;
+ bits<8> LIT;
bits<7> Function = fun;
- let isTwoAddress = 1;
+// let isTwoAddress = 1;
let Inst{25-21} = Ra;
let Inst{20-13} = LIT;
let Inst{12} = 1;
}
//3.3.4
-class FPForm<bits<6> opcode, bits<11> fun, string asmstr>
- : InstAlpha<opcode, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), asmstr> {
- bits<5> Fc;
- bits<5> Fa;
- bits<5> Fb;
- bits<11> Function = fun;
-
- let Inst{25-21} = Fa;
- let Inst{20-16} = Fb;
- let Inst{15-5} = Function;
- let Inst{4-0} = Fc;
-}
+class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
+ let Pattern = pattern;
-class FPFormCM<bits<6> opcode, bits<11> fun, dag OL, string asmstr>
- : InstAlpha<opcode, OL, asmstr> {
bits<5> Fc;
bits<5> Fa;
bits<5> Fb;
}
//3.3.5
-class PALForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
+class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
+ : InstAlpha<opcode, asmstr, itin> {
+ let OutOperandList = (ops);
+ let InOperandList = OL;
bits<26> Function;
let Inst{25-0} = Function;
// Pseudo instructions.
-class PseudoInstAlpha<dag OL, string nm> : InstAlpha<0, OL, nm> {
+class PseudoInstAlpha<dag OOL, dag IOL, string nm, list<dag> pattern, InstrItinClass itin>
+ : InstAlpha<0, nm, itin> {
+ let OutOperandList = OOL;
+ let InOperandList = IOL;
+ let Pattern = pattern;
+
}