Misc. SSE2 intrinsics: clflush, lfench, mfence

[oota-llvm.git] / lib / Target / Alpha / AlphaInstrInfo.cpp

diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index fc9ace7126a7289e59f2ec69ec16da06351be493..c30f38aee3a0cacc02f733909e5855d8109729b8 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -26,7 +26,11 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
                                  unsigned& sourceReg,
                                  unsigned& destReg) const {
   MachineOpCode oc = MI.getOpcode();
-  if (oc == Alpha::BIS || oc == Alpha::CPYSS || oc == Alpha::CPYST) {
+  if (oc == Alpha::BIS    || 
+      oc == Alpha::CPYSS  || 
+      oc == Alpha::CPYST  ||
+      oc == Alpha::CPYSSt || 
+      oc == Alpha::CPYSTs) {
     // or r1, r2, r2 
     // cpys(s|t) r1 r2 r2
     assert(MI.getNumOperands() == 3 &&
@@ -42,3 +46,40 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
   }
   return false;
 }
+
+unsigned 
+AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
+  switch (MI->getOpcode()) {
+  case Alpha::LDL:
+  case Alpha::LDQ:
+  case Alpha::LDBU:
+  case Alpha::LDWU:
+  case Alpha::LDS:
+  case Alpha::LDT:
+    if (MI->getOperand(1).isFrameIndex()) {
+      FrameIndex = MI->getOperand(1).getFrameIndex();
+      return MI->getOperand(0).getReg();
+    }
+    break;
+  }
+  return 0;
+}
+
+unsigned 
+AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
+  switch (MI->getOpcode()) {
+  case Alpha::STL:
+  case Alpha::STQ:
+  case Alpha::STB:
+  case Alpha::STW:
+  case Alpha::STS:
+  case Alpha::STT:
+    if (MI->getOperand(1).isFrameIndex()) {
+      FrameIndex = MI->getOperand(1).getFrameIndex();
+      return MI->getOperand(0).getReg();
+    }
+    break;
+  }
+  return 0;
+}
+