Patch up omissions in DebugLoc propagation.

[oota-llvm.git] / lib / Target / Alpha / AlphaInstrInfo.td

diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index 664dae59c2768578ff890d9e1f4d2175c65c7be8..28f3d1e33bc13b3a5fc41fd606ae1912d6dbb60e 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -93,7 +93,8 @@ def immSExt16int  : PatLeaf<(imm), [{ //(int)imm fits in a 16 bit sign extended
 }], SExt16>;
 
 def zappat : PatFrag<(ops node:$LHS), (and node:$LHS, imm:$L), [{
-  ConstantSDNode *RHS = cast<ConstantSDNode>(N->getOperand(1));
+  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  if (!RHS) return 0;
   uint64_t build = get_zapImm(N->getOperand(0), (uint64_t)RHS->getZExtValue());
   return build != 0;
 }]>;
@@ -151,10 +152,10 @@ def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>;
 let hasCtrlDep = 1, Defs = [R30], Uses = [R30] in {
 def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt),
                 "; ADJUP $amt", 
-                [(callseq_start imm:$amt)], s_pseudo>;
+                [(callseq_start timm:$amt)], s_pseudo>;
 def ADJUSTSTACKDOWN : PseudoInstAlpha<(outs), (ins s64imm:$amt1, s64imm:$amt2),
                 "; ADJDOWN $amt1",
-                [(callseq_end imm:$amt1, imm:$amt2)], s_pseudo>;
+                [(callseq_end timm:$amt1, timm:$amt2)], s_pseudo>;
 }
 
 def ALTENT : PseudoInstAlpha<(outs), (ins s64imm:$TARGET), "$$$TARGET..ng:\n", [], s_pseudo>;
@@ -569,7 +570,9 @@ def : Pat<(truncstorei8 GPRC:$DATA, GPRC:$addr),
 
 
 //load address, rellocated gpdist form
-let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
+let OutOperandList = (ops GPRC:$RA),
+    InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM),
+    mayLoad = 1 in {
 def LDAg  : MForm<0x08, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;  //Load address
 def LDAHg : MForm<0x09, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;  //Load address
 }
@@ -588,7 +591,9 @@ let OutOperandList = (outs GPRC:$RR),
 def STQ_C : MForm<0x2F, 0, "stq_l $RA,$DISP($RB)", [], s_ist>;
 def STL_C : MForm<0x2E, 0, "stl_l $RA,$DISP($RB)", [], s_ist>;
 }
-let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
+let OutOperandList = (ops GPRC:$RA),
+    InOperandList = (ops s64imm:$DISP, GPRC:$RB),
+    mayLoad = 1 in {
 def LDQ_L : MForm<0x2B, 1, "ldq_l $RA,$DISP($RB)", [], s_ild>;
 def LDL_L : MForm<0x2A, 1, "ldl_l $RA,$DISP($RB)", [], s_ild>;
 }
@@ -856,6 +861,7 @@ def FBNE : br_fcc<0x36, "fbne">;
 //An ugly trick to get the opcode as an imm I can use
 def immBRCond : SDNodeXForm<imm, [{
   switch((uint64_t)N->getZExtValue()) {
+    default: assert(0 && "Unknown branch type");
     case 0:  return getI64Imm(Alpha::BEQ);
     case 1:  return getI64Imm(Alpha::BNE);
     case 2:  return getI64Imm(Alpha::BGE);
@@ -870,7 +876,6 @@ def immBRCond : SDNodeXForm<imm, [{
     case 23: return getI64Imm(Alpha::FBGT);
     case 24: return getI64Imm(Alpha::FBLE);
     case 25: return getI64Imm(Alpha::FBLT);
-    default: assert(0 && "Unknown branch type");
   }
 }]>;