Move DebugInfo checks into EmitComments and remove them from

[oota-llvm.git] / lib / Target / Alpha / AlphaLLRP.cpp

diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp
index 79d03c66457fc5afad00e05be02e3b149bf30188..0c51bc554be949e8d2893577a3a1acf436115f11 100644 (file)
--- a/lib/Target/Alpha/AlphaLLRP.cpp
+++ b/lib/Target/Alpha/AlphaLLRP.cpp
@@ -39,7 +39,7 @@ namespace {
 
     static char ID;
     AlphaLLRPPass(AlphaTargetMachine &tm) 
-      : MachineFunctionPass((intptr_t)&ID), TM(tm) { }
+      : MachineFunctionPass(&ID), TM(tm) { }
 
     virtual const char *getPassName() const {
       return "Alpha NOP inserter";
@@ -49,6 +49,7 @@ namespace {
       const TargetInstrInfo *TII = F.getTarget().getInstrInfo();
       bool Changed = false;
       MachineInstr* prev[3] = {0,0,0};
+      DebugLoc dl = DebugLoc::getUnknownLoc();
       unsigned count = 0;
       for (MachineFunction::iterator FI = F.begin(), FE = F.end();
            FI != FE; ++FI) {
@@ -67,15 +68,13 @@ namespace {
           case Alpha::STW:  case Alpha::STB:
           case Alpha::STT: case Alpha::STS:
            if (MI->getOperand(2).getReg() == Alpha::R30) {
-             if (prev[0] 
-                 && prev[0]->getOperand(2).getReg() == 
-                 MI->getOperand(2).getReg()
-                 && prev[0]->getOperand(1).getImmedValue() == 
-                 MI->getOperand(1).getImmedValue()) {
+             if (prev[0] && 
+                 prev[0]->getOperand(2).getReg() == MI->getOperand(2).getReg()&&
+                 prev[0]->getOperand(1).getImm() == MI->getOperand(1).getImm()){
                prev[0] = prev[1];
                prev[1] = prev[2];
                prev[2] = 0;
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
                  .addReg(Alpha::R31)
                  .addReg(Alpha::R31); 
                Changed = true; nopintro += 1;
@@ -83,14 +82,14 @@ namespace {
              } else if (prev[1] 
                         && prev[1]->getOperand(2).getReg() == 
                         MI->getOperand(2).getReg()
-                        && prev[1]->getOperand(1).getImmedValue() == 
-                        MI->getOperand(1).getImmedValue()) {
+                        && prev[1]->getOperand(1).getImm() == 
+                        MI->getOperand(1).getImm()) {
                prev[0] = prev[2];
                prev[1] = prev[2] = 0;
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
                  .addReg(Alpha::R31)
                  .addReg(Alpha::R31); 
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
                  .addReg(Alpha::R31)
                  .addReg(Alpha::R31);
                Changed = true; nopintro += 2;
@@ -98,15 +97,15 @@ namespace {
              } else if (prev[2] 
                         && prev[2]->getOperand(2).getReg() == 
                         MI->getOperand(2).getReg()
-                        && prev[2]->getOperand(1).getImmedValue() == 
-                        MI->getOperand(1).getImmedValue()) {
+                        && prev[2]->getOperand(1).getImm() == 
+                        MI->getOperand(1).getImm()) {
                prev[0] = prev[1] = prev[2] = 0;
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                 .addReg(Alpha::R31);
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                 .addReg(Alpha::R31);
-               BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
-                 .addReg(Alpha::R31);
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31).addReg(Alpha::R31);
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31).addReg(Alpha::R31);
+               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
+                 .addReg(Alpha::R31).addReg(Alpha::R31);
                Changed = true; nopintro += 3;
                count += 3;
              }
@@ -122,9 +121,6 @@ namespace {
           case Alpha::ALTENT:
           case Alpha::MEMLABEL:
           case Alpha::PCLABEL:
-          case Alpha::IDEF_I:
-          case Alpha::IDEF_F32:
-          case Alpha::IDEF_F64:
             --count;
             break;
           case Alpha::BR:
@@ -141,7 +137,7 @@ namespace {
         if (ub || AlignAll) {
           //we can align stuff for free at this point
           while (count % 4) {
-            BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
+            BuildMI(MBB, MBB.end(), dl, TII->get(Alpha::BISr), Alpha::R31)
               .addReg(Alpha::R31).addReg(Alpha::R31);
             ++count;
             ++nopalign;