Patch up omissions in DebugLoc propagation.

[oota-llvm.git] / lib / Target / Alpha / AlphaLLRP.cpp

diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp
index 6d2d243e3d0f3f3af0b873aff380014697aec012..7a1b78497b829775e7a83ee2b3d0327faf37bb3e 100644 (file)
--- a/lib/Target/Alpha/AlphaLLRP.cpp
+++ b/lib/Target/Alpha/AlphaLLRP.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by Andrew Lenharth and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -37,7 +37,9 @@ namespace {
     ///
     AlphaTargetMachine &TM;
 
-    AlphaLLRPPass(AlphaTargetMachine &tm) : TM(tm) { }
+    static char ID;
+    AlphaLLRPPass(AlphaTargetMachine &tm) 
+      : MachineFunctionPass(&ID), TM(tm) { }
 
     virtual const char *getPassName() const {
       return "Alpha NOP inserter";
@@ -65,11 +67,9 @@ namespace {
           case Alpha::STW:  case Alpha::STB:
           case Alpha::STT: case Alpha::STS:
            if (MI->getOperand(2).getReg() == Alpha::R30) {
-             if (prev[0] 
-                 && prev[0]->getOperand(2).getReg() == 
-                 MI->getOperand(2).getReg()
-                 && prev[0]->getOperand(1).getImmedValue() == 
-                 MI->getOperand(1).getImmedValue()) {
+             if (prev[0] && 
+                 prev[0]->getOperand(2).getReg() == MI->getOperand(2).getReg()&&
+                 prev[0]->getOperand(1).getImm() == MI->getOperand(1).getImm()){
                prev[0] = prev[1];
                prev[1] = prev[2];
                prev[2] = 0;
@@ -81,8 +81,8 @@ namespace {
              } else if (prev[1] 
                         && prev[1]->getOperand(2).getReg() == 
                         MI->getOperand(2).getReg()
-                        && prev[1]->getOperand(1).getImmedValue() == 
-                        MI->getOperand(1).getImmedValue()) {
+                        && prev[1]->getOperand(1).getImm() == 
+                        MI->getOperand(1).getImm()) {
                prev[0] = prev[2];
                prev[1] = prev[2] = 0;
                BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
@@ -96,8 +96,8 @@ namespace {
              } else if (prev[2] 
                         && prev[2]->getOperand(2).getReg() == 
                         MI->getOperand(2).getReg()
-                        && prev[2]->getOperand(1).getImmedValue() == 
-                        MI->getOperand(1).getImmedValue()) {
+                        && prev[2]->getOperand(1).getImm() == 
+                        MI->getOperand(1).getImm()) {
                prev[0] = prev[1] = prev[2] = 0;
                BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
                  .addReg(Alpha::R31);
@@ -120,9 +120,6 @@ namespace {
           case Alpha::ALTENT:
           case Alpha::MEMLABEL:
           case Alpha::PCLABEL:
-          case Alpha::IDEF_I:
-          case Alpha::IDEF_F32:
-          case Alpha::IDEF_F64:
             --count;
             break;
           case Alpha::BR:
@@ -152,6 +149,7 @@ namespace {
       return Changed;
     }
   };
+  char AlphaLLRPPass::ID = 0;
 } // end of anonymous namespace
 
 FunctionPass *llvm::createAlphaLLRPPass(AlphaTargetMachine &tm) {