Patch up omissions in DebugLoc propagation.

[oota-llvm.git] / lib / Target / Alpha / AlphaLLRP.cpp

diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp
index 79d03c66457fc5afad00e05be02e3b149bf30188..7a1b78497b829775e7a83ee2b3d0327faf37bb3e 100644 (file)
--- a/lib/Target/Alpha/AlphaLLRP.cpp
+++ b/lib/Target/Alpha/AlphaLLRP.cpp
@@ -39,7 +39,7 @@ namespace {
 
     static char ID;
     AlphaLLRPPass(AlphaTargetMachine &tm) 
-      : MachineFunctionPass((intptr_t)&ID), TM(tm) { }
+      : MachineFunctionPass(&ID), TM(tm) { }
 
     virtual const char *getPassName() const {
       return "Alpha NOP inserter";
@@ -67,11 +67,9 @@ namespace {
           case Alpha::STW:  case Alpha::STB:
           case Alpha::STT: case Alpha::STS:
            if (MI->getOperand(2).getReg() == Alpha::R30) {
-             if (prev[0] 
-                 && prev[0]->getOperand(2).getReg() == 
-                 MI->getOperand(2).getReg()
-                 && prev[0]->getOperand(1).getImmedValue() == 
-                 MI->getOperand(1).getImmedValue()) {
+             if (prev[0] && 
+                 prev[0]->getOperand(2).getReg() == MI->getOperand(2).getReg()&&
+                 prev[0]->getOperand(1).getImm() == MI->getOperand(1).getImm()){
                prev[0] = prev[1];
                prev[1] = prev[2];
                prev[2] = 0;
@@ -83,8 +81,8 @@ namespace {
              } else if (prev[1] 
                         && prev[1]->getOperand(2).getReg() == 
                         MI->getOperand(2).getReg()
-                        && prev[1]->getOperand(1).getImmedValue() == 
-                        MI->getOperand(1).getImmedValue()) {
+                        && prev[1]->getOperand(1).getImm() == 
+                        MI->getOperand(1).getImm()) {
                prev[0] = prev[2];
                prev[1] = prev[2] = 0;
                BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
@@ -98,8 +96,8 @@ namespace {
              } else if (prev[2] 
                         && prev[2]->getOperand(2).getReg() == 
                         MI->getOperand(2).getReg()
-                        && prev[2]->getOperand(1).getImmedValue() == 
-                        MI->getOperand(1).getImmedValue()) {
+                        && prev[2]->getOperand(1).getImm() == 
+                        MI->getOperand(1).getImm()) {
                prev[0] = prev[1] = prev[2] = 0;
                BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
                  .addReg(Alpha::R31);
@@ -122,9 +120,6 @@ namespace {
           case Alpha::ALTENT:
           case Alpha::MEMLABEL:
           case Alpha::PCLABEL:
-          case Alpha::IDEF_I:
-          case Alpha::IDEF_F32:
-          case Alpha::IDEF_F64:
             --count;
             break;
           case Alpha::BR: