Allow the specification of explicit alignments for constant pool entries.

[oota-llvm.git] / lib / Target / Alpha / AlphaRegisterInfo.td

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.td b/lib/Target/Alpha/AlphaRegisterInfo.td
index 416500293780881f697089a9bb2b616fa7ac1ed7..febf6fe2ff55952fa98322f5f5ce6c6386cae24e 100644 (file)
--- a/lib/Target/Alpha/AlphaRegisterInfo.td
+++ b/lib/Target/Alpha/AlphaRegisterInfo.td
@@ -1,4 +1,4 @@
-//===- AlphaRegisterInfo.td - The Alpha Register File --*- tablegen -*-===//
+//===- AlphaRegisterInfo.td - The Alpha Register File ------*- tablegen -*-===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
@@ -7,6 +7,7 @@
 // 
 //===----------------------------------------------------------------------===//
 //
+// This file describes the Alpha register set.
 //
 //===----------------------------------------------------------------------===//
 
@@ -77,17 +78,63 @@ def F30 : FPR<30, "$f30">;  def F31 : FPR<31, "$f31">;
   // $28 is undefined after any and all calls
 
 /// Register classes
-def GPRC : RegisterClass<i64, 64,
-//Volitle
-     [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R27,
-//Non-Volitile
-     R9, R10, R11, R12, R13, R14, R15, R26, /*R28,*/ R29, /* R30, R31*/ ]>;
-//R28 is reserved for the assembler
+def GPRC : RegisterClass<"Alpha", [i64], 64,
+     // Volatile
+     [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
+      R23, R24, R25, R28, 
+     //Special meaning, but volatile
+     R27, //procedure address
+     R26, //return address
+     R29, //global offset table address
+     // Non-volatile
+     R9, R10, R11, R12, R13, R14,
+// Don't allocate 15, 30, 31
+     R15, R30, R31 ]> //zero
+{
+  let MethodProtos = [{
+    iterator allocation_order_end(MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    GPRCClass::iterator
+    GPRCClass::allocation_order_end(MachineFunction &MF) const {
+        return end()-3;
+    }
+  }];
+}
 
-//Don't allocate 15, 29, 30, 31
-//Allocation volatiles only for now
-def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, 
-       F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
-       F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30]>;
+def F4RC : RegisterClass<"Alpha", [f32], 64, [F0, F1, 
+        F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
+        F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
+        // Saved:
+        F2, F3, F4, F5, F6, F7, F8, F9,
+        F31 ]> //zero
+{
+  let MethodProtos = [{
+    iterator allocation_order_end(MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    F4RCClass::iterator
+    F4RCClass::allocation_order_end(MachineFunction &MF) const {
+        return end()-1;
+    }
+  }];
+}
 
+def F8RC : RegisterClass<"Alpha", [f64], 64, [F0, F1, 
+        F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
+        F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
+        // Saved:
+        F2, F3, F4, F5, F6, F7, F8, F9,
+        F31 ]> //zero
+{
+  let MethodProtos = [{
+    iterator allocation_order_end(MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    F8RCClass::iterator
+    F8RCClass::allocation_order_end(MachineFunction &MF) const {
+        return end()-1;
+    }
+  }];
+}