Allow the specification of explicit alignments for constant pool entries.

[oota-llvm.git] / lib / Target / Alpha / AlphaRegisterInfo.td

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.td b/lib/Target/Alpha/AlphaRegisterInfo.td
index b0884360861ab198d751582be354d92408748d2a..febf6fe2ff55952fa98322f5f5ce6c6386cae24e 100644 (file)
--- a/lib/Target/Alpha/AlphaRegisterInfo.td
+++ b/lib/Target/Alpha/AlphaRegisterInfo.td
@@ -78,7 +78,7 @@ def F30 : FPR<30, "$f30">;  def F31 : FPR<31, "$f31">;
   // $28 is undefined after any and all calls
 
 /// Register classes
-def GPRC : RegisterClass<"Alpha", i64, 64,
+def GPRC : RegisterClass<"Alpha", [i64], 64,
      // Volatile
      [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
       R23, R24, R25, R28, 
@@ -102,7 +102,7 @@ def GPRC : RegisterClass<"Alpha", i64, 64,
   }];
 }
 
-def F4RC : RegisterClass<"Alpha", f32, 64, [F0, F1, 
+def F4RC : RegisterClass<"Alpha", [f32], 64, [F0, F1, 
         F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
         F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
         // Saved:
@@ -120,7 +120,7 @@ def F4RC : RegisterClass<"Alpha", f32, 64, [F0, F1,
   }];
 }
 
-def F8RC : RegisterClass<"Alpha", f64, 64, [F0, F1, 
+def F8RC : RegisterClass<"Alpha", [f64], 64, [F0, F1, 
         F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
         F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
         // Saved: