Introduce new headers whose inclusion forces linking and
[oota-llvm.git] / lib / Target / Alpha / AlphaTargetMachine.cpp
index 8f263294052099a5d377bd95b43a2d9b326da2f0..66f72577044e049fe172a5b28fd5c29fc5213b60 100644 (file)
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 
 #include "Alpha.h"
 #include "AlphaJITInfo.h"
+#include "AlphaTargetAsmInfo.h"
 #include "AlphaTargetMachine.h"
 #include "llvm/Module.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetOptions.h"
+#include "llvm/PassManager.h"
 #include "llvm/Target/TargetMachineRegistry.h"
-#include "llvm/Transforms/Scalar.h"
-#include "llvm/Support/Debug.h"
-#include <iostream>
+#include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
-namespace {
-  // Register the targets
-  RegisterTarget<AlphaTargetMachine> X("alpha", "  Alpha (incomplete)");
-}
+/// AlphaTargetMachineModule - Note that this is used on hosts that cannot link
+/// in a library unless there are references into the library.  In particular,
+/// it seems that it is not possible to get things to work on Win32 without
+/// this.  Though it is unused, do not remove it.
+extern "C" int AlphaTargetMachineModule;
+int AlphaTargetMachineModule = 0;
+
+// Register the targets
+static RegisterTarget<AlphaTargetMachine> X("alpha", "Alpha [experimental]");
 
+// Force static initialization when called from llvm/InitializeAllTargets.h
 namespace llvm {
-  cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha",
-                             cl::desc("Enable LSR for Alpha (beta option!)"),
-                             cl::Hidden);
+  void InitializeAlphaTarget() { }
+}
+
+const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const {
+  return new AlphaTargetAsmInfo(*this);
 }
 
 unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) {
@@ -40,6 +46,8 @@ unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) {
   if (TT.size() >= 5 && TT[0] == 'a' && TT[1] == 'l' && TT[2] == 'p' &&
       TT[3] == 'h' && TT[4] == 'a')
     return 20;
+  // If the target triple is something non-alpha, we don't match.
+  if (!TT.empty()) return 0;
 
   if (M.getEndianness()  == Module::LittleEndian &&
       M.getPointerSize() == Module::Pointer64)
@@ -48,7 +56,7 @@ unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) {
            M.getPointerSize() != Module::AnyPointerSize)
     return 0;                                    // Match for some other target
 
-  return 0;
+  return getJITMatchQuality()/2;
 }
 
 unsigned AlphaTargetMachine::getJITMatchQuality() {
@@ -59,102 +67,65 @@ unsigned AlphaTargetMachine::getJITMatchQuality() {
 #endif
 }
 
-AlphaTargetMachine::AlphaTargetMachine(const Module &M, IntrinsicLowering *IL,
-                                       const std::string &FS)
-  : TargetMachine("alpha", IL, true),
+AlphaTargetMachine::AlphaTargetMachine(const Module &M, const std::string &FS)
+  : DataLayout("e-f128:128:128"),
     FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
     JITInfo(*this),
-    Subtarget(M, FS)
-{
-  DEBUG(std::cerr << "FS is " << FS << "\n");
+    Subtarget(M, FS),
+    TLInfo(*this) {
+  setRelocationModel(Reloc::PIC_);
 }
 
-/// addPassesToEmitFile - Add passes to the specified pass manager to implement
-/// a static compiler for this target.
-///
-bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM,
-                                             std::ostream &Out,
-                                             CodeGenFileType FileType) {
-  if (FileType != TargetMachine::AssemblyFile) return true;
-
-  if (EnableAlphaLSR) {
-    PM.add(createLoopStrengthReducePass());
-    PM.add(createCFGSimplificationPass());
-  }
-
-  // FIXME: Implement efficient support for garbage collection intrinsics.
-  PM.add(createLowerGCPass());
-
-  // FIXME: Implement the invoke/unwind instructions!
-  PM.add(createLowerInvokePass());
-
-  // FIXME: Implement the switch instruction in the instruction selector!
-  PM.add(createLowerSwitchPass());
-
-  // Make sure that no unreachable blocks are instruction selected.
-  PM.add(createUnreachableBlockEliminationPass());
-
-  PM.add(createAlphaPatternInstructionSelector(*this));
 
-  if (PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
-  PM.add(createRegisterAllocator());
-
-  if (PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
-  PM.add(createPrologEpilogCodeInserter());
-
-  // Must run branch selection immediately preceding the asm printer
-  //PM.add(createAlphaBranchSelectionPass());
-
-  PM.add(createAlphaCodePrinterPass(Out, *this));
+//===----------------------------------------------------------------------===//
+// Pass Pipeline Configuration
+//===----------------------------------------------------------------------===//
 
-  PM.add(createMachineCodeDeleter());
+bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
+                                         CodeGenOpt::Level OptLevel) {
+  PM.add(createAlphaISelDag(*this));
   return false;
 }
-
-void AlphaJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
-
-  if (EnableAlphaLSR) {
-    PM.add(createLoopStrengthReducePass());
-    PM.add(createCFGSimplificationPass());
-  }
-
-  // FIXME: Implement efficient support for garbage collection intrinsics.
-  PM.add(createLowerGCPass());
-
-  // FIXME: Implement the invoke/unwind instructions!
-  PM.add(createLowerInvokePass());
-
-  // FIXME: Implement the switch instruction in the instruction selector!
-  PM.add(createLowerSwitchPass());
-
-  // Make sure that no unreachable blocks are instruction selected.
-  PM.add(createUnreachableBlockEliminationPass());
-
-  PM.add(createAlphaPatternInstructionSelector(TM));
-
-  if (PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
-  PM.add(createRegisterAllocator());
-
-  if (PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
-  PM.add(createPrologEpilogCodeInserter());
-
+bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
+                                        CodeGenOpt::Level OptLevel) {
   // Must run branch selection immediately preceding the asm printer
-  //PM.add(createAlphaBranchSelectionPass());
-
+  PM.add(createAlphaBranchSelectionPass());
+  return false;
 }
-
-bool AlphaTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
-                                                    MachineCodeEmitter &MCE) {
-  PM.add(createAlphaCodeEmitterPass(MCE));
-  // Delete machine code for this function
-  PM.add(createMachineCodeDeleter());
+bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
+                                            CodeGenOpt::Level OptLevel,
+                                            bool Verbose,
+                                            raw_ostream &Out) {
+  PM.add(createAlphaLLRPPass(*this));
+  PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
+  return false;
+}
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
+                                        CodeGenOpt::Level OptLevel,
+                                        bool DumpAsm, MachineCodeEmitter &MCE) {
+  PM.add(createAlphaCodeEmitterPass(*this, MCE));
+  if (DumpAsm)
+    PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel, true));
   return false;
 }
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
+                                        CodeGenOpt::Level OptLevel,
+                                        bool DumpAsm, JITCodeEmitter &JCE) {
+  PM.add(createAlphaJITCodeEmitterPass(*this, JCE));
+  if (DumpAsm)
+    PM.add(createAlphaCodePrinterPass(errs(), *this, OptLevel, true));
+  return false;
+}
+bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+                                              CodeGenOpt::Level OptLevel,
+                                              bool DumpAsm,
+                                              MachineCodeEmitter &MCE) {
+  return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
+}
+bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+                                              CodeGenOpt::Level OptLevel,
+                                              bool DumpAsm,
+                                              JITCodeEmitter &JCE) {
+  return addCodeEmitter(PM, OptLevel, DumpAsm, JCE);
+}
+