//===----------------------------------------------------------------------===//
#include "Blackfin.h"
-#include "BlackfinISelLowering.h"
#include "BlackfinTargetMachine.h"
#include "BlackfinRegisterInfo.h"
#include "llvm/Intrinsics.h"
BlackfinDAGToDAGISel(BlackfinTargetMachine &TM, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(TM, OptLevel) {}
- virtual void InstructionSelect();
+ virtual void PostprocessISelDAG();
virtual const char *getPassName() const {
return "Blackfin DAG->DAG Pattern Instruction Selection";
#include "BlackfinGenDAGISel.inc"
private:
- SDNode *Select(SDValue Op);
- bool SelectADDRspii(SDValue Op, SDValue Addr,
- SDValue &Base, SDValue &Offset);
+ SDNode *Select(SDNode *N);
+ bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
// Walk the DAG after instruction selection, fixing register class issues.
void FixRegisterClasses(SelectionDAG &DAG);
return new BlackfinDAGToDAGISel(TM, OptLevel);
}
-/// InstructionSelect - This callback is invoked by
-/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
-void BlackfinDAGToDAGISel::InstructionSelect() {
- // Select target instructions for the DAG.
- SelectRoot(*CurDAG);
- DEBUG(errs() << "Selected selection DAG before regclass fixup:\n");
- DEBUG(CurDAG->dump());
+void BlackfinDAGToDAGISel::PostprocessISelDAG() {
FixRegisterClasses(*CurDAG);
}
-SDNode *BlackfinDAGToDAGISel::Select(SDValue Op) {
- SDNode *N = Op.getNode();
- DebugLoc dl = N->getDebugLoc();
+SDNode *BlackfinDAGToDAGISel::Select(SDNode *N) {
if (N->isMachineOpcode())
return NULL; // Already selected.
}
}
- return SelectCode(Op);
+ return SelectCode(N);
}
-bool BlackfinDAGToDAGISel::SelectADDRspii(SDValue Op,
- SDValue Addr,
+bool BlackfinDAGToDAGISel::SelectADDRspii(SDValue Addr,
SDValue &Base,
SDValue &Offset) {
FrameIndexSDNode *FIN = 0;
SDValue Val) {
SmallVector<SDValue, 8> ops(N->op_begin(), N->op_end());
ops[Num] = Val;
- SDValue New = DAG.UpdateNodeOperands(SDValue(N, 0), ops.data(), ops.size());
- DAG.ReplaceAllUsesWith(N, New.getNode());
+ SDNode *New = DAG.UpdateNodeOperands(N, ops.data(), ops.size());
+ DAG.ReplaceAllUsesWith(N, New);
}
// After instruction selection, insert COPY_TO_REGCLASS nodes to help in
// We cannot copy CC <-> !(CC/D)
if ((isCC(DefRC) && !isDCC(UseRC)) || (isCC(UseRC) && !isDCC(DefRC))) {
SDNode *Copy =
- DAG.getTargetNode(TargetInstrInfo::COPY_TO_REGCLASS,
- NI->getDebugLoc(),
- MVT::i32,
- UI.getUse().get(),
- DAG.getTargetConstant(BF::DRegClassID, MVT::i32));
+ DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
+ NI->getDebugLoc(),
+ MVT::i32,
+ UI.getUse().get(),
+ DAG.getTargetConstant(BF::DRegClassID, MVT::i32));
UpdateNodeOperand(DAG, *UI, UI.getOperandNo(), SDValue(Copy, 0));
}
}