Add a quick pass to optimize sign / zero extension instructions. For targets where...

[oota-llvm.git] / lib / Target / CellSPU / README.txt

diff --git a/lib/Target/CellSPU/README.txt b/lib/Target/CellSPU/README.txt
index c10937616e132c5913e4af20e36e2484ada4d53e..4783dd5d24eb22fd150b5a09bfacdfd59978233b 100644 (file)
--- a/lib/Target/CellSPU/README.txt
+++ b/lib/Target/CellSPU/README.txt
@@ -8,6 +8,7 @@ Department in The Aerospace Corporation:
 - Mark Thomas (floating point instructions)
 - Michael AuYeung (intrinsics)
 - Chandler Carruth (LLVM expertise)
+- Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise)
 
 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
@@ -18,24 +19,72 @@ OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
 LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
 REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
 OR PUNITIVE  DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
-SUCH DAMAGES ARE FORESEEABLE. 
+SUCH DAMAGES ARE FORESEEABLE.
 
 ---------------------------------------------------------------------------
+--WARNING--:
 --WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
+--WARNING--:
+
+If you are brave enough to try this code or help to hack on it, be sure
+to add 'spu' to configure's --enable-targets option, e.g.:
+
+        ./configure <your_configure_flags_here> \
+           --enable-targets=x86,x86_64,powerpc,spu
+
 ---------------------------------------------------------------------------
 
 TODO:
-* Finish branch instructions, branch prediction
+* Create a machine pass for performing dual-pipeline scheduling specifically
+  for CellSPU, and insert branch prediction instructions as needed.
+
+* i32 instructions:
+
+  * i32 division (work-in-progress)
+
+* i64 support (see i64operations.c test harness):
+
+  * shifts and comparison operators: done
+  * sign and zero extension: done
+  * addition: done
+  * subtraction: needed
+  * multiplication: done
+
+* i128 support:
+
+  * zero extension, any extension: done
+  * sign extension: needed
+  * arithmetic operators (add, sub, mul, div): needed
+  * logical operations (and, or, shl, srl, sra, xor, nor, nand): needed
+
+    * or: done
+
+* f64 support
 
-  These instructions were started, but only insofar as to get llvm-gcc-4.2's
-  crtbegin.ll working (which doesn't.)
+  * Comparison operators:
+    SETOEQ              unimplemented
+    SETOGT              unimplemented
+    SETOGE              unimplemented
+    SETOLT              unimplemented
+    SETOLE              unimplemented
+    SETONE              unimplemented
+    SETO                done (lowered)
+    SETUO               done (lowered)
+    SETUEQ              unimplemented
+    SETUGT              unimplemented
+    SETUGE              unimplemented
+    SETULT              unimplemented
+    SETULE              unimplemented
+    SETUNE              unimplemented
 
-* Double floating point support
+* LLVM vector suport
 
-  This was started. "What's missing?" to be filled in.
+  * VSETCC needs to be implemented. It's pretty straightforward to code, but
+    needs implementation.
 
 * Intrinsics
 
-  Lots of progress. "What's missing/incomplete?" to be filled in.
+  * spu.h instrinsics added but not tested. Need to have an operational
+    llvm-spu-gcc in order to write a unit test harness.
 
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