Update the .cvs files.

[oota-llvm.git] / lib / Target / CellSPU / SPUISelLowering.h

diff --git a/lib/Target/CellSPU/SPUISelLowering.h b/lib/Target/CellSPU/SPUISelLowering.h
index d5bfac4ca75bde8c498f075383bdaceeaa30fa38..5c41c29c51571d3dd39532f56a427350712e030d 100644 (file)
--- a/lib/Target/CellSPU/SPUISelLowering.h
+++ b/lib/Target/CellSPU/SPUISelLowering.h
@@ -62,8 +62,13 @@ namespace llvm {
       ROTBYTES_RIGHT_S,         ///< Vector rotate right, by bytes, sign fill
       ROTBYTES_LEFT,            ///< Rotate bytes (loads -> ROTQBYI)
       ROTBYTES_LEFT_CHAINED,    ///< Rotate bytes (loads -> ROTQBYI), with chain
-      FSMBI,                    ///< Form Select Mask for Bytes, Immediate
+      ROTBYTES_LEFT_BITS,       ///< Rotate bytes left by bit shift count
+      SELECT_MASK,              ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
       SELB,                     ///< Select bits -> (b & mask) | (a & ~mask)
+      ADD_EXTENDED,             ///< Add extended, with carry
+      CARRY_GENERATE,           ///< Carry generate for ADD_EXTENDED
+      SUB_EXTENDED,             ///< Subtract extended, with borrow
+      BORROW_GENERATE,          ///< Borrow generate for SUB_EXTENDED
       FPInterp,                 ///< Floating point interpolate
       FPRecipEst,               ///< Floating point reciprocal estimate
       SEXT32TO64,               ///< Sign-extended 32-bit const -> 64-bits
@@ -74,15 +79,15 @@ namespace llvm {
   /// Predicates that are used for node matching:
   namespace SPU {
     SDOperand get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
-                             MVT::ValueType ValueType);
+                             MVT ValueType);
     SDOperand get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
-                             MVT::ValueType ValueType);
+                             MVT ValueType);
     SDOperand get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
-                             MVT::ValueType ValueType);
+                             MVT ValueType);
     SDOperand get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
-                            MVT::ValueType ValueType);
+                            MVT ValueType);
     SDOperand get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
-                              MVT::ValueType ValueType);
+                              MVT ValueType);
     SDOperand get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
     SDOperand get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
   }
@@ -104,7 +109,7 @@ namespace llvm {
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
     /// getSetCCResultType - Return the ValueType for ISD::SETCC
-    virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
+    virtual MVT getSetCCResultType(const SDOperand &) const;
     
     /// LowerOperation - Provide custom lowering hooks for some operations.
     ///
@@ -123,11 +128,11 @@ namespace llvm {
 
     std::pair<unsigned, const TargetRegisterClass*> 
       getRegForInlineAsmConstraint(const std::string &Constraint,
-                                   MVT::ValueType VT) const;
+                                   MVT VT) const;
 
     void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
                                       std::vector<SDOperand> &Ops,
-                                      SelectionDAG &DAG);
+                                      SelectionDAG &DAG) const;
 
     /// isLegalAddressImmediate - Return true if the integer value can be used
     /// as the offset of the target addressing mode.