VEC2PREFSLOT, ///< Extract element 0
SHLQUAD_L_BITS, ///< Rotate quad left, by bits
SHLQUAD_L_BYTES, ///< Rotate quad left, by bytes
- VEC_SHL, ///< Vector shift left
- VEC_SRL, ///< Vector shift right (logical)
- VEC_SRA, ///< Vector shift right (arithmetic)
VEC_ROTL, ///< Vector rotate left
VEC_ROTR, ///< Vector rotate right
ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI)
ROTBYTES_LEFT_BITS, ///< Rotate bytes left by bit shift count
SELECT_MASK, ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
SELB, ///< Select bits -> (b & mask) | (a & ~mask)
- ADD_EXTENDED, ///< Add extended, with carry
- CARRY_GENERATE, ///< Carry generate for ADD_EXTENDED
- SUB_EXTENDED, ///< Subtract extended, with borrow
- BORROW_GENERATE, ///< Borrow generate for SUB_EXTENDED
+ // Markers: These aren't used to generate target-dependent nodes, but
+ // are used during instruction selection.
+ ADD64_MARKER, ///< i64 addition marker
+ SUB64_MARKER, ///< i64 subtraction marker
+ MUL64_MARKER, ///< i64 multiply marker
LAST_SPUISD ///< Last user-defined instruction
};
}
- /// Predicates that are used for node matching:
+ //! Utility functions specific to CellSPU:
namespace SPU {
SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType);
+ EVT ValueType);
SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType);
+ EVT ValueType);
SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType);
+ EVT ValueType);
SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType);
+ EVT ValueType);
SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType);
+ EVT ValueType);
SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
+
+ SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
+ const SPUTargetMachine &TM);
+ //! Simplify a EVT::v2i64 constant splat to CellSPU-ready form
+ SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat,
+ DebugLoc dl);
}
class SPUTargetMachine; // forward dec'l.
public TargetLowering
{
int VarArgsFrameIndex; // FrameIndex for start of varargs area.
- int ReturnAddrIndex; // FrameIndex for return slot.
SPUTargetMachine &SPUTM;
public:
+ //! The venerable constructor
+ /*!
+ This is where the CellSPU backend sets operation handling (i.e., legal,
+ custom, expand or promote.)
+ */
SPUTargetLowering(SPUTargetMachine &TM);
+ //! Get the target machine
+ SPUTargetMachine &getSPUTargetMachine() {
+ return SPUTM;
+ }
+
/// getTargetNodeName() - This method returns the name of a target specific
/// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ValueType for ISD::SETCC
- virtual MVT getSetCCResultType(MVT VT) const;
+ virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
//! Custom lowering hooks
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const;
+ EVT VT) const;
void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
bool hasMemory,
virtual bool isLegalAddressImmediate(GlobalValue *) const;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
+
+ /// getFunctionAlignment - Return the Log2 alignment of this function.
+ virtual unsigned getFunctionAlignment(const Function *F) const;
+
+ virtual SDValue
+ LowerFormalArguments(SDValue Chain,
+ CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins,
+ DebugLoc dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals);
+
+ virtual SDValue
+ LowerCall(SDValue Chain, SDValue Callee,
+ CallingConv::ID CallConv, bool isVarArg,
+ bool isTailCall,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<ISD::InputArg> &Ins,
+ DebugLoc dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals);
+
+ virtual SDValue
+ LowerReturn(SDValue Chain,
+ CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ DebugLoc dl, SelectionDAG &DAG);
};
}