Update the .cvs files.

[oota-llvm.git] / lib / Target / CellSPU / SPUInstrInfo.cpp

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 64f6225f707e0a95b21e6e779d93980b34f4da5c..3e991a9e79c9cc3f9344aeb6e490062af6320a37 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -17,7 +17,7 @@
 #include "SPUTargetMachine.h"
 #include "SPUGenInstrInfo.inc"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
-#include <iostream>
+#include "llvm/Support/Streams.h"
 
 using namespace llvm;
 
@@ -49,14 +49,13 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
     break;
   case SPU::ORIv4i32:
   case SPU::ORIr32:
-  case SPU::ORIr64:
   case SPU::ORHIv8i16:
   case SPU::ORHIr16:
-  case SPU::ORHI1To2:
+  case SPU::ORHIi8i16:
   case SPU::ORBIv16i8:
   case SPU::ORBIr8:
-  case SPU::ORI2To4:
-  case SPU::ORI1To4:
+  case SPU::ORIi16i32:
+  case SPU::ORIi8i32:
   case SPU::AHIvec:
   case SPU::AHIr16:
   case SPU::AIvec:
@@ -103,7 +102,6 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
   case SPU::ORr64:
   case SPU::ORf32:
   case SPU::ORf64:
-  case SPU::ORgprc:
     assert(MI.getNumOperands() == 3 &&
            MI.getOperand(0).isRegister() &&
            MI.getOperand(1).isRegister() &&
@@ -188,10 +186,15 @@ void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
                                    const TargetRegisterClass *DestRC,
                                    const TargetRegisterClass *SrcRC) const
 {
-  if (DestRC != SrcRC) {
-    cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
-    abort();
-  }
+  // We support cross register class moves for our aliases, such as R3 in any
+  // reg class to any other reg class containing R3.  This is required because
+  // we instruction select bitconvert i64 -> f64 as a noop for example, so our
+  // types have no specific meaning.
+  
+  //if (DestRC != SrcRC) {
+  //  cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
+  //  abort();
+  //}
 
   if (DestRC == SPU::R8CRegisterClass) {
     BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);
@@ -203,18 +206,19 @@ void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
     BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg)
       .addReg(SrcReg);
   } else if (DestRC == SPU::R64CRegisterClass) {
-    BuildMI(MBB, MI, get(SPU::ORIr64), DestReg).addReg(SrcReg).addImm(0);
+    BuildMI(MBB, MI, get(SPU::ORr64), DestReg).addReg(SrcReg)
+      .addReg(SrcReg);
   } else if (DestRC == SPU::R64FPRegisterClass) {
     BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg)
       .addReg(SrcReg);
-  } else if (DestRC == SPU::GPRCRegisterClass) {
+  } /* else if (DestRC == SPU::GPRCRegisterClass) {
     BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg)
       .addReg(SrcReg);
-  } else if (DestRC == SPU::VECREGRegisterClass) {
+  } */ else if (DestRC == SPU::VECREGRegisterClass) {
     BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
       .addReg(SrcReg);
   } else {
-    std::cerr << "Attempt to copy unknown/unsupported register class!\n";
+    cerr << "Attempt to copy unknown/unsupported register class!\n";
     abort();
   }
 }