Add Thumb-2 support for TEQ amd TST.

[oota-llvm.git] / lib / Target / CellSPU / SPUInstrInfo.h

diff --git a/lib/Target/CellSPU/SPUInstrInfo.h b/lib/Target/CellSPU/SPUInstrInfo.h
index 7bbdfada12c793d3ff32e074c923d0b2bdfb4aec..ffb40875ff10316a143fc55a59ad1eab905ebfb6 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.h
+++ b/lib/Target/CellSPU/SPUInstrInfo.h
@@ -45,10 +45,6 @@ namespace llvm {
     ///
     virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
 
-    /// getPointerRegClass - Return the register class to use to hold pointers.
-    /// This is used for addressing modes.
-    virtual const TargetRegisterClass *getPointerRegClass() const;
-
     /// Return true if the instruction is a register to register move and return
     /// the source and dest operands and their sub-register indices by reference.
     virtual bool isMoveInstr(const MachineInstr &MI,
@@ -103,14 +99,15 @@ namespace llvm {
     bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
 
     virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
-                              MachineBasicBlock *&FBB,
-                              SmallVectorImpl<MachineOperand> &Cond) const;
+                               MachineBasicBlock *&FBB,
+                               SmallVectorImpl<MachineOperand> &Cond,
+                               bool AllowModify) const;
 
     virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
 
     virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
-                             MachineBasicBlock *FBB,
-                             const SmallVectorImpl<MachineOperand> &Cond) const;
+                              MachineBasicBlock *FBB,
+                              const SmallVectorImpl<MachineOperand> &Cond) const;
    };
 }