Fix ARM memory operand parsing of post indexing with just a base register, that

[oota-llvm.git] / lib / Target / CellSPU / SPUInstrInfo.td

diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td
index 63eb85a2921e6f937ccdf5fa7a9e2ee0bd90386a..09849da45ae27a0a4debd0fce9568a296bb1d46c 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/lib/Target/CellSPU/SPUInstrInfo.td
@@ -4430,13 +4430,6 @@ def : Pat<(v4i32 v4i32Imm:$imm),
 def : Pat<(i8 imm:$imm),
           (ILHr8 imm:$imm)>;
 
-//===----------------------------------------------------------------------===//
-// Call instruction patterns:
-//===----------------------------------------------------------------------===//
-// Return void
-def : Pat<(ret),
-          (RET)>;
-
 //===----------------------------------------------------------------------===//
 // Zero/Any/Sign extensions
 //===----------------------------------------------------------------------===//