Add Thumb-2 support for TEQ amd TST.

[oota-llvm.git] / lib / Target / CellSPU / SPUOperands.td

diff --git a/lib/Target/CellSPU/SPUOperands.td b/lib/Target/CellSPU/SPUOperands.td
index 43982279b52059d30e9575bfffd619e9f2b73de0..802628f8996550ecdc0f57cb2f61a0d0087ea10b 100644 (file)
--- a/lib/Target/CellSPU/SPUOperands.td
+++ b/lib/Target/CellSPU/SPUOperands.td
@@ -575,7 +575,7 @@ def calltarget : Operand<iPTR> {
   let MIOperandInfo = (ops u18imm:$calldest);
 }
 
-// Relative call target
+// PC relative call target
 def relcalltarget : Operand<iPTR> {
   let PrintMethod = "printPCRelativeOperand";
   let MIOperandInfo = (ops s16imm:$calldest);
@@ -586,6 +586,11 @@ def brtarget : Operand<OtherVT> {
   let PrintMethod = "printPCRelativeOperand";
 }
 
+// Hint for branch target
+def hbrtarget : Operand<OtherVT> {
+  let PrintMethod = "printHBROperand";
+}
+
 // Indirect call target
 def indcalltarget : Operand<iPTR> {
   let PrintMethod = "printCallOperand";
@@ -604,15 +609,15 @@ def symbolLSA: Operand<i32> {
   let PrintMethod = "printSymbolLSA";
 }
 
-// memory s7imm(reg) operaand
-def memri7 : Operand<iPTR> {
-  let PrintMethod = "printMemRegImmS7";
+// Shuffle address memory operaand [s7imm(reg) d-format]
+def shufaddr : Operand<iPTR> {
+  let PrintMethod = "printShufAddr";
   let MIOperandInfo = (ops s7imm:$imm, ptr_rc:$reg);
 }
 
 // memory s10imm(reg) operand
-def memri10 : Operand<iPTR> {
-  let PrintMethod = "printMemRegImmS10";
+def dformaddr : Operand<iPTR> {
+  let PrintMethod = "printDFormAddr";
   let MIOperandInfo = (ops s10imm:$imm, ptr_rc:$reg);
 }