// simm7 predicate - True if the immediate fits in an 7-bit signed
// field.
def simm7: PatLeaf<(imm), [{
- int sextVal = int(N->getSignExtended());
+ int sextVal = int(N->getSExtValue());
return (sextVal >= -64 && sextVal <= 63);
}]>;
// immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
// field.
def immSExt8 : PatLeaf<(imm), [{
- int Value = int(N->getSignExtended());
+ int Value = int(N->getSExtValue());
return (Value >= -(1 << 8) && Value <= (1 << 8) - 1);
}]>;
let MIOperandInfo = (ops u18imm:$calldest);
}
-// Relative call target
+// PC relative call target
def relcalltarget : Operand<iPTR> {
let PrintMethod = "printPCRelativeOperand";
let MIOperandInfo = (ops s16imm:$calldest);
let PrintMethod = "printPCRelativeOperand";
}
+// Hint for branch target
+def hbrtarget : Operand<OtherVT> {
+ let PrintMethod = "printHBROperand";
+}
+
// Indirect call target
def indcalltarget : Operand<iPTR> {
let PrintMethod = "printCallOperand";
let PrintMethod = "printSymbolLSA";
}
-// memory s7imm(reg) operaand
-def memri7 : Operand<iPTR> {
- let PrintMethod = "printMemRegImmS7";
+// Shuffle address memory operaand [s7imm(reg) d-format]
+def shufaddr : Operand<iPTR> {
+ let PrintMethod = "printShufAddr";
let MIOperandInfo = (ops s7imm:$imm, ptr_rc:$reg);
}
// memory s10imm(reg) operand
-def memri10 : Operand<iPTR> {
- let PrintMethod = "printMemRegImmS10";
+def dformaddr : Operand<iPTR> {
+ let PrintMethod = "printDFormAddr";
let MIOperandInfo = (ops s10imm:$imm, ptr_rc:$reg);
}