//
// The LLVM Compiler Infrastructure
//
-// This file was developed by a team from the Computer Systems Research
-// Department at The Aerospace Corporation and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
// Cell SPU Instruction Operands:
// simm7 predicate - True if the immediate fits in an 7-bit signed
// field.
def simm7: PatLeaf<(imm), [{
- int sextVal = ((((int) N->getValue()) << 25) >> 25);
+ int sextVal = int(N->getSignExtended());
return (sextVal >= -64 && sextVal <= 63);
}]>;
// immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
// field.
def immSExt8 : PatLeaf<(imm), [{
- int Value = (int) N->getValue();
- int Value8 = (Value << 24) >> 24;
- return (Value < 0xff && (Value8 >= -128 && Value8 < 127));
+ int Value = int(N->getSignExtended());
+ return (Value >= -(1 << 8) && Value <= (1 << 8) - 1);
}]>;
// immU8: immediate, unsigned 8-bit quantity
return isI32IntS10Immediate(N);
}]>;
-// i16ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign
+// i32ImmUns10 predicate - True if the i32 immediate fits in a 10-bit unsigned
+// field. Used by RI10Form instructions like 'ldq'.
+def i32ImmUns10 : PatLeaf<(imm), [{
+ return isI32IntU10Immediate(N);
+}]>;
+
+// i16ImmSExt10 predicate - True if the i16 immediate fits in a 10-bit sign
// extended field. Used by RI10Form instructions like 'ldq'.
def i16ImmSExt10 : PatLeaf<(imm), [{
return isI16IntS10Immediate(N);
}]>;
+// i16ImmUns10 predicate - True if the i16 immediate fits into a 10-bit unsigned
+// value. Used by RI10Form instructions.
+def i16ImmUns10 : PatLeaf<(imm), [{
+ return isI16IntU10Immediate(N);
+}]>;
+
def immSExt16 : PatLeaf<(imm), [{
// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
// field.
return ((Value & ((1 << 19) - 1)) == Value);
}]>;
+def lo16 : PatLeaf<(imm), [{
+ // lo16 predicate - returns true if the immediate has all zeros in the
+ // low order bits and is a 32-bit constant:
+ if (N->getValueType(0) == MVT::i32) {
+ uint32_t val = N->getValue();
+ return ((val & 0x0000ffff) == val);
+ }
+
+ return false;
+}], LO16>;
+
def hi16 : PatLeaf<(imm), [{
// hi16 predicate - returns true if the immediate has all zeros in the
// low order bits and is a 32-bit constant:
if (N->getValueType(0) == MVT::i32) {
- uint32_t val = N->getValue();
+ uint32_t val = uint32_t(N->getValue());
return ((val & 0xffff0000) == val);
+ } else if (N->getValueType(0) == MVT::i64) {
+ uint64_t val = N->getValue();
+ return ((val & 0xffff0000ULL) == val);
}
return false;
}], HI16>;
+def bitshift : PatLeaf<(imm), [{
+ // bitshift predicate - returns true if 0 < imm <= 7 for SHLQBII
+ // (shift left quadword by bits immediate)
+ int64_t Val = N->getValue();
+ return (Val > 0 && Val <= 7);
+}]>;
+
//===----------------------------------------------------------------------===//
// Floating point operands:
//===----------------------------------------------------------------------===//
// Transform a float, returning the high 16 bits shifted down, as if
// the float was really an unsigned integer:
def HI16_f32 : SDNodeXForm<fpimm, [{
- const APFloat &apf = N->getValueAPF();
- float fval = apf.convertToFloat();
- unsigned val = *((unsigned *) &fval);
- return getI32Imm(val >> 16);
+ float fval = N->getValueAPF().convertToFloat();
+ return getI32Imm(FloatToBits(fval) >> 16);
}]>;
// Transformation function on floats: get the low 16 bits as if the float was
// an unsigned integer.
def LO16_f32 : SDNodeXForm<fpimm, [{
- const APFloat &apf = N->getValueAPF();
- float fval = apf.convertToFloat();
- unsigned val = *((unsigned *) &fval);
- return getI32Imm(val & 0xffff);
+ float fval = N->getValueAPF().convertToFloat();
+ return getI32Imm(FloatToBits(fval) & 0xffff);
}]>;
def FPimm_sext16 : SDNodeXForm<fpimm, [{
- const APFloat &apf = N->getValueAPF();
- float fval = apf.convertToFloat();
- unsigned val = *((unsigned *) &fval);
- return getI32Imm((int) ((val << 16) >> 16));
+ float fval = N->getValueAPF().convertToFloat();
+ return getI32Imm((int) ((FloatToBits(fval) << 16) >> 16));
}]>;
def FPimm_u18 : SDNodeXForm<fpimm, [{
- const APFloat &apf = N->getValueAPF();
- float fval = apf.convertToFloat();
- unsigned val = *((unsigned *) &fval);
- return getI32Imm(val & ((1 << 19) - 1));
+ float fval = N->getValueAPF().convertToFloat();
+ return getI32Imm(FloatToBits(fval) & ((1 << 19) - 1));
}]>;
def fpimmSExt16 : PatLeaf<(fpimm), [{
// Does the SFP constant only have upp 16 bits set?
def hi16_f32 : PatLeaf<(fpimm), [{
if (N->getValueType(0) == MVT::f32) {
- const APFloat &apf = N->getValueAPF();
- float fval = apf.convertToFloat();
- uint32_t val = *((unsigned *) &fval);
+ uint32_t val = FloatToBits(N->getValueAPF().convertToFloat());
return ((val & 0xffff0000) == val);
}
// Does the SFP constant fit into 18 bits?
def fpimm18 : PatLeaf<(fpimm), [{
if (N->getValueType(0) == MVT::f32) {
- const APFloat &apf = N->getValueAPF();
- float fval = apf.convertToFloat();
- uint32_t Value = *((uint32_t *) &fval);
+ uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
return ((Value & ((1 << 19) - 1)) == Value);
}
}], FPimm_u18>;
//===----------------------------------------------------------------------===//
-// 64-bit operands:
+// 64-bit operands (TODO):
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
}], v8i16SExt10Imm_xform>;
+// v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
+// immediate constant load for v8i16 vectors.
+def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
+}]>;
+
+// v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
+// load, works in conjunction with its transform function.
+def v8i16Uns10Imm: PatLeaf<(build_vector), [{
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
+}], v8i16Uns10Imm_xform>;
+
// v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v8i16 vectors.
-def v8i16SExt16Imm_xform: SDNodeXForm<build_vector, [{
+def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
}]>;
// load, works in conjunction with its transform function.
def v8i16SExt16Imm: PatLeaf<(build_vector), [{
return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
-}], v8i16SExt16Imm_xform>;
+}], v8i16Uns16Imm_xform>;
// v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
// immediate constant load for v4i32 vectors.
return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
}], v4i32SExt10Imm_xform>;
+// v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
+// immediate constant load for v4i32 vectors.
+def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
+}]>;
+
+// v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
+// load, works in conjunction with its transform function.
+def v4i32Uns10Imm: PatLeaf<(build_vector), [{
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
+}], v4i32Uns10Imm_xform>;
+
// v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v4i32 vectors.
def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
//===----------------------------------------------------------------------===//
// Operand Definitions.
-def s7imm: Operand<i16> {
+def s7imm: Operand<i8> {
+ let PrintMethod = "printS7ImmOperand";
+}
+
+def s7imm_i8: Operand<i8> {
let PrintMethod = "printS7ImmOperand";
}
let PrintMethod = "printU7ImmOperand";
}
+def u7imm_i8: Operand<i8> {
+ let PrintMethod = "printU7ImmOperand";
+}
+
def u7imm_i32: Operand<i32> {
let PrintMethod = "printU7ImmOperand";
}
let PrintMethod = "printS10ImmOperand";
}
+def s10imm_i8: Operand<i8> {
+ let PrintMethod = "printS10ImmOperand";
+}
+
def s10imm_i32: Operand<i32> {
let PrintMethod = "printS10ImmOperand";
}
let PrintMethod = "printU10ImmOperand";
}
+def u10imm_i8: Operand<i8> {
+ let PrintMethod = "printU10ImmOperand";
+}
+
def u10imm_i32: Operand<i32> {
let PrintMethod = "printU10ImmOperand";
}
let PrintMethod = "printS16ImmOperand";
}
+def s16imm_i8: Operand<i8> {
+ let PrintMethod = "printS16ImmOperand";
+}
+
def s16imm_i32: Operand<i32> {
let PrintMethod = "printS16ImmOperand";
}
let PrintMethod = "printS16ImmOperand";
}
-def u16imm : Operand<i32> {
+def u16imm_i64 : Operand<i64> {
+ let PrintMethod = "printU16ImmOperand";
+}
+
+def u16imm_i32 : Operand<i32> {
+ let PrintMethod = "printU16ImmOperand";
+}
+
+def u16imm : Operand<i16> {
let PrintMethod = "printU16ImmOperand";
}
let PrintMethod = "printROTNeg7Imm";
}
-// Floating point immediate operands
-def f32imm : Operand<f32>;
+def rotNeg7imm_i8 : Operand<i8> {
+ let PrintMethod = "printROTNeg7Imm";
+}
def target : Operand<OtherVT> {
let PrintMethod = "printBranchOperand";
projects / oota-llvm.git / blobdiff