Update the .cvs files.

[oota-llvm.git] / lib / Target / CellSPU / SPUOperands.td

diff --git a/lib/Target/CellSPU/SPUOperands.td b/lib/Target/CellSPU/SPUOperands.td
index 6f079eab64756c12ceff2e6867d3b716eaa1288f..d17faac861fbfc3142e181b4fa3345ff0cc13122 100644 (file)
--- a/lib/Target/CellSPU/SPUOperands.td
+++ b/lib/Target/CellSPU/SPUOperands.td
@@ -2,9 +2,8 @@
 // 
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by a team from the Computer Systems Research
-// Department at The Aerospace Corporation and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
 // Cell SPU Instruction Operands:
@@ -64,7 +63,7 @@ def HI16_vec : SDNodeXForm<scalar_to_vector, [{
 // simm7 predicate - True if the immediate fits in an 7-bit signed
 // field.
 def simm7: PatLeaf<(imm), [{
-  int sextVal = ((((int) N->getValue()) << 25) >> 25);
+  int sextVal = int(N->getSignExtended());
   return (sextVal >= -64 && sextVal <= 63);
 }]>;
 
@@ -77,9 +76,8 @@ def uimm7: PatLeaf<(imm), [{
 // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
 // field.
 def immSExt8  : PatLeaf<(imm), [{
-  int Value = (int) N->getValue();
-  int Value8 = (Value << 24) >> 24;
-  return (Value < 0xff && (Value8 >= -128 && Value8 < 127));
+  int Value = int(N->getSignExtended());
+  return (Value >= -(1 << 8) && Value <= (1 << 8) - 1);
 }]>;
 
 // immU8: immediate, unsigned 8-bit quantity
@@ -99,15 +97,21 @@ def i32ImmSExt10  : PatLeaf<(imm), [{
   return isI32IntS10Immediate(N);
 }]>;
 
+// i32ImmUns10 predicate - True if the i32 immediate fits in a 10-bit unsigned
+// field.  Used by RI10Form instructions like 'ldq'.
+def i32ImmUns10  : PatLeaf<(imm), [{
+  return isI32IntU10Immediate(N);
+}]>;
+
 // i16ImmSExt10 predicate - True if the i16 immediate fits in a 10-bit sign
 // extended field.  Used by RI10Form instructions like 'ldq'.
 def i16ImmSExt10  : PatLeaf<(imm), [{
   return isI16IntS10Immediate(N);
 }]>;
 
-// i16ImmU10 predicate - True if the i16 immediate fits into a 10-bit unsigned
+// i16ImmUns10 predicate - True if the i16 immediate fits into a 10-bit unsigned
 // value. Used by RI10Form instructions.
-def i16ImmU10 : PatLeaf<(imm), [{
+def i16ImmUns10 : PatLeaf<(imm), [{
   return isI16IntU10Immediate(N);
 }]>;
 
@@ -135,17 +139,38 @@ def imm18  : PatLeaf<(imm), [{
   return ((Value & ((1 << 19) - 1)) == Value);
 }]>;
 
+def lo16 : PatLeaf<(imm), [{
+  // lo16 predicate - returns true if the immediate has all zeros in the
+  // low order bits and is a 32-bit constant:
+  if (N->getValueType(0) == MVT::i32) {
+    uint32_t val = N->getValue();
+    return ((val & 0x0000ffff) == val);
+  }
+
+  return false;
+}], LO16>;
+
 def hi16 : PatLeaf<(imm), [{
   // hi16 predicate - returns true if the immediate has all zeros in the
   // low order bits and is a 32-bit constant:
   if (N->getValueType(0) == MVT::i32) {
-    uint32_t val = N->getValue();
+    uint32_t val = uint32_t(N->getValue());
     return ((val & 0xffff0000) == val);
+  } else if (N->getValueType(0) == MVT::i64) {
+    uint64_t val = N->getValue();
+    return ((val & 0xffff0000ULL) == val);
   }
 
   return false;
 }], HI16>;
 
+def bitshift : PatLeaf<(imm), [{
+  // bitshift predicate - returns true if 0 < imm <= 7 for SHLQBII
+  // (shift left quadword by bits immediate)
+  int64_t Val = N->getValue();
+  return (Val > 0 && Val <= 7);
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Floating point operands:
 //===----------------------------------------------------------------------===//
@@ -261,9 +286,21 @@ def v8i16SExt10Imm: PatLeaf<(build_vector), [{
   return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
 }], v8i16SExt10Imm_xform>;
 
+// v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
+// immediate constant load for v8i16 vectors.
+def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
+  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
+}]>;
+
+// v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
+// load, works in conjunction with its transform function.
+def v8i16Uns10Imm: PatLeaf<(build_vector), [{
+  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
+}], v8i16Uns10Imm_xform>;
+
 // v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
 // immediate constant load for v8i16 vectors.
-def v8i16SExt16Imm_xform: SDNodeXForm<build_vector, [{
+def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
   return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
 }]>;
 
@@ -271,7 +308,7 @@ def v8i16SExt16Imm_xform: SDNodeXForm<build_vector, [{
 // load, works in conjunction with its transform function.
 def v8i16SExt16Imm: PatLeaf<(build_vector), [{
   return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
-}], v8i16SExt16Imm_xform>;
+}], v8i16Uns16Imm_xform>;
 
 // v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
 // immediate constant load for v4i32 vectors.
@@ -285,6 +322,18 @@ def v4i32SExt10Imm: PatLeaf<(build_vector), [{
   return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
 }], v4i32SExt10Imm_xform>;
 
+// v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
+// immediate constant load for v4i32 vectors.
+def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
+  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
+}]>;
+
+// v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
+// load, works in conjunction with its transform function.
+def v4i32Uns10Imm: PatLeaf<(build_vector), [{
+  return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
+}], v4i32Uns10Imm_xform>;
+
 // v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
 // immediate constant load for v4i32 vectors.
 def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
@@ -382,7 +431,11 @@ def v2i64Imm: PatLeaf<(build_vector), [{
 //===----------------------------------------------------------------------===//
 // Operand Definitions.
 
-def s7imm: Operand<i16> {
+def s7imm: Operand<i8> {
+  let PrintMethod = "printS7ImmOperand";
+}
+
+def s7imm_i8: Operand<i8> {
   let PrintMethod = "printS7ImmOperand";
 }
 
@@ -390,6 +443,10 @@ def u7imm: Operand<i16> {
   let PrintMethod = "printU7ImmOperand";
 }
 
+def u7imm_i8: Operand<i8> {
+  let PrintMethod = "printU7ImmOperand";
+}
+
 def u7imm_i32: Operand<i32> {
   let PrintMethod = "printU7ImmOperand";
 }
@@ -399,6 +456,10 @@ def s10imm : Operand<i16> {
   let PrintMethod = "printS10ImmOperand";
 }
 
+def s10imm_i8: Operand<i8> {
+  let PrintMethod = "printS10ImmOperand";
+}
+
 def s10imm_i32: Operand<i32> {
   let PrintMethod = "printS10ImmOperand";
 }
@@ -412,6 +473,10 @@ def u10imm: Operand<i16> {
   let PrintMethod = "printU10ImmOperand";
 }
 
+def u10imm_i8: Operand<i8> {
+  let PrintMethod = "printU10ImmOperand";
+}
+
 def u10imm_i32: Operand<i32> {
   let PrintMethod = "printU10ImmOperand";
 }
@@ -420,6 +485,10 @@ def s16imm  : Operand<i16> {
   let PrintMethod = "printS16ImmOperand";
 }
 
+def s16imm_i8: Operand<i8> {
+  let PrintMethod = "printS16ImmOperand";
+}
+
 def s16imm_i32: Operand<i32> {
   let PrintMethod = "printS16ImmOperand";
 }
@@ -436,7 +505,15 @@ def s16imm_f64: Operand<f64> {
   let PrintMethod = "printS16ImmOperand";
 }
 
-def u16imm : Operand<i32> {
+def u16imm_i64 : Operand<i64> {
+  let PrintMethod = "printU16ImmOperand";
+}
+
+def u16imm_i32 : Operand<i32> {
+  let PrintMethod = "printU16ImmOperand";
+}
+
+def u16imm : Operand<i16> {
   let PrintMethod = "printU16ImmOperand";
 }
 
@@ -482,8 +559,9 @@ def rotNeg7imm_i16 : Operand<i16> {
   let PrintMethod = "printROTNeg7Imm";
 }
 
-// Floating point immediate operands
-def f32imm : Operand<f32>;
+def rotNeg7imm_i8 : Operand<i8> {
+  let PrintMethod = "printROTNeg7Imm";
+}
 
 def target : Operand<OtherVT> {
   let PrintMethod = "printBranchOperand";