Update the .cvs files.

[oota-llvm.git] / lib / Target / CellSPU / SPUOperands.td

diff --git a/lib/Target/CellSPU/SPUOperands.td b/lib/Target/CellSPU/SPUOperands.td
index 94271428c8547717b07a965320d23dd124073ed0..d17faac861fbfc3142e181b4fa3345ff0cc13122 100644 (file)
--- a/lib/Target/CellSPU/SPUOperands.td
+++ b/lib/Target/CellSPU/SPUOperands.td
@@ -76,9 +76,8 @@ def uimm7: PatLeaf<(imm), [{
 // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
 // field.
 def immSExt8  : PatLeaf<(imm), [{
-  int Value = (int) N->getValue();
-  int Value8 = (Value << 24) >> 24;
-  return (Value < 0xff && (Value8 >= -128 && Value8 < 127));
+  int Value = int(N->getSignExtended());
+  return (Value >= -(1 << 8) && Value <= (1 << 8) - 1);
 }]>;
 
 // immU8: immediate, unsigned 8-bit quantity
@@ -141,7 +140,7 @@ def imm18  : PatLeaf<(imm), [{
 }]>;
 
 def lo16 : PatLeaf<(imm), [{
-  // hi16 predicate - returns true if the immediate has all zeros in the
+  // lo16 predicate - returns true if the immediate has all zeros in the
   // low order bits and is a 32-bit constant:
   if (N->getValueType(0) == MVT::i32) {
     uint32_t val = N->getValue();
@@ -155,8 +154,11 @@ def hi16 : PatLeaf<(imm), [{
   // hi16 predicate - returns true if the immediate has all zeros in the
   // low order bits and is a 32-bit constant:
   if (N->getValueType(0) == MVT::i32) {
-    uint32_t val = N->getValue();
+    uint32_t val = uint32_t(N->getValue());
     return ((val & 0xffff0000) == val);
+  } else if (N->getValueType(0) == MVT::i64) {
+    uint64_t val = N->getValue();
+    return ((val & 0xffff0000ULL) == val);
   }
 
   return false;
@@ -503,7 +505,15 @@ def s16imm_f64: Operand<f64> {
   let PrintMethod = "printS16ImmOperand";
 }
 
-def u16imm : Operand<i32> {
+def u16imm_i64 : Operand<i64> {
+  let PrintMethod = "printU16ImmOperand";
+}
+
+def u16imm_i32 : Operand<i32> {
+  let PrintMethod = "printU16ImmOperand";
+}
+
+def u16imm : Operand<i16> {
   let PrintMethod = "printU16ImmOperand";
 }
 
@@ -549,6 +559,10 @@ def rotNeg7imm_i16 : Operand<i16> {
   let PrintMethod = "printROTNeg7Imm";
 }
 
+def rotNeg7imm_i8 : Operand<i8> {
+  let PrintMethod = "printROTNeg7Imm";
+}
+
 def target : Operand<OtherVT> {
   let PrintMethod = "printBranchOperand";
 }