Update the .cvs files.

[oota-llvm.git] / lib / Target / CellSPU / SPURegisterInfo.cpp

diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp
index 90606cb37fdd769572ee970a51417aa920decc46..b6b7fd3174159be0d69100e0319e1f6d5eb3f0f7 100644 (file)
--- a/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file contains the Cell implementation of the MRegisterInfo class.
+// This file contains the Cell implementation of the TargetRegisterInfo class.
 //
 //===----------------------------------------------------------------------===//
 
@@ -40,7 +40,6 @@
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include <cstdlib>
-#include <iostream>
 
 using namespace llvm;
 
@@ -178,7 +177,7 @@ unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
   case SPU::R126: return 126;
   case SPU::R127: return 127;
   default:
-    std::cerr << "Unhandled reg in SPURegisterInfo::getRegisterNumbering!\n";
+    cerr << "Unhandled reg in SPURegisterInfo::getRegisterNumbering!\n";
     abort();
   }
 }
@@ -191,15 +190,6 @@ SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
 {
 }
 
-void SPURegisterInfo::reMaterialize(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator I,
-                                    unsigned DestReg,
-                                    const MachineInstr *Orig) const {
-  MachineInstr *MI = Orig->clone();
-  MI->getOperand(0).setReg(DestReg);
-  MBB.insert(I, MI);
-}
-
 // SPU's 128-bit registers used for argument passing:
 static const unsigned SPU_ArgRegs[] = {
   SPU::R3,  SPU::R4,  SPU::R5,  SPU::R6,  SPU::R7,  SPU::R8,  SPU::R9,
@@ -221,7 +211,7 @@ SPURegisterInfo::getArgRegs()
   return SPU_ArgRegs;
 }
 
-const unsigned
+unsigned
 SPURegisterInfo::getNumArgRegs()
 {
   return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
@@ -289,9 +279,9 @@ SPURegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
  */
 BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
-  Reserved.set(SPU::R0);               // LR
-  Reserved.set(SPU::R1);               // SP
-  Reserved.set(SPU::R2);               // environment pointer
+  Reserved.set(SPU::R0);                // LR
+  Reserved.set(SPU::R1);                // SP
+  Reserved.set(SPU::R2);                // environment pointer
   return Reserved;
 }
 
@@ -331,7 +321,7 @@ SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
 
 void
 SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
-                                    RegScavenger *RS) const
+                                     RegScavenger *RS) const
 {
   unsigned i = 0;
   MachineInstr &MI = *II;
@@ -454,7 +444,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
     if (hasDebugInfo) {
       // Mark effective beginning of when frame pointer becomes valid.
       FrameLabelId = MMI->NextLabelID();
-      BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(FrameLabelId);
+      BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(FrameLabelId).addImm(0);
     }
   
     // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
@@ -464,10 +454,10 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
     if (isS10Constant(FrameSize)) {
       // Spill $sp to adjusted $sp
       BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
-       .addReg(SPU::R1);
+        .addReg(SPU::R1);
       // Adjust $sp by required amout
       BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
-       .addImm(FrameSize);
+        .addImm(FrameSize);
     } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
       // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
       // $r2 to adjust $sp:
@@ -475,7 +465,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
         .addImm(-16)
         .addReg(SPU::R1);
       BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
-       .addImm(FrameSize);
+        .addImm(FrameSize);
       BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1)
         .addReg(SPU::R2)
         .addReg(SPU::R1);
@@ -504,17 +494,17 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
       // Add callee saved registers to move list.
       const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
       for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
-       int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
-       unsigned Reg = CSI[I].getReg();
-       if (Reg == SPU::R0) continue;
-       MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
-       MachineLocation CSSrc(Reg);
-       Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
+        int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
+        unsigned Reg = CSI[I].getReg();
+        if (Reg == SPU::R0) continue;
+        MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
+        MachineLocation CSSrc(Reg);
+        Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
       }
     
       // Mark effective beginning of when frame pointer is ready.
       unsigned ReadyLabelId = MMI->NextLabelID();
-      BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(ReadyLabelId);
+      BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(ReadyLabelId).addImm(0);
     
       MachineLocation FPDst(SPU::R1);
       MachineLocation FPSrc(MachineLocation::VirtualFP);
@@ -528,7 +518,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
       MachineBasicBlock::iterator MBBI = prior(MBB.end());
       // Insert terminator label
       unsigned BranchLabelId = MMI->NextLabelID();
-      BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(BranchLabelId);
+      BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(BranchLabelId).addImm(0);
     }
   }
 }
@@ -556,7 +546,7 @@ SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
         .addReg(SPU::R1);
       BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1)
         .addReg(SPU::R1)
-       .addImm(FrameSize);
+        .addImm(FrameSize);
     } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
       // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
       // $r2 to adjust $sp:
@@ -564,7 +554,7 @@ SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
         .addImm(16)
         .addReg(SPU::R1);
       BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
-       .addImm(FrameSize);
+        .addImm(FrameSize);
       BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
         .addReg(SPU::R1)
         .addReg(SPU::R2);